2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 /* ----------------------------------------------------------------- */
51 mult_t core_csb_ratio
;
55 corecnf_t corecnf_tab
[] = {
56 {_byp
, _byp
}, /* 0x00 */
57 {_byp
, _byp
}, /* 0x01 */
58 {_byp
, _byp
}, /* 0x02 */
59 {_byp
, _byp
}, /* 0x03 */
60 {_byp
, _byp
}, /* 0x04 */
61 {_byp
, _byp
}, /* 0x05 */
62 {_byp
, _byp
}, /* 0x06 */
63 {_byp
, _byp
}, /* 0x07 */
64 {_1x
, _x2
}, /* 0x08 */
65 {_1x
, _x4
}, /* 0x09 */
66 {_1x
, _x8
}, /* 0x0A */
67 {_1x
, _x8
}, /* 0x0B */
68 {_1_5x
, _x2
}, /* 0x0C */
69 {_1_5x
, _x4
}, /* 0x0D */
70 {_1_5x
, _x8
}, /* 0x0E */
71 {_1_5x
, _x8
}, /* 0x0F */
72 {_2x
, _x2
}, /* 0x10 */
73 {_2x
, _x4
}, /* 0x11 */
74 {_2x
, _x8
}, /* 0x12 */
75 {_2x
, _x8
}, /* 0x13 */
76 {_2_5x
, _x2
}, /* 0x14 */
77 {_2_5x
, _x4
}, /* 0x15 */
78 {_2_5x
, _x8
}, /* 0x16 */
79 {_2_5x
, _x8
}, /* 0x17 */
80 {_3x
, _x2
}, /* 0x18 */
81 {_3x
, _x4
}, /* 0x19 */
82 {_3x
, _x8
}, /* 0x1A */
83 {_3x
, _x8
}, /* 0x1B */
86 /* ----------------------------------------------------------------- */
93 volatile immap_t
*im
= (immap_t
*) CFG_IMMR
;
98 u32 corecnf_tab_index
;
103 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
108 #ifdef CONFIG_MPC834X
113 #if !defined(CONFIG_MPC832X)
116 #if defined(CONFIG_MPC8315)
119 #if defined(CONFIG_MPC837X)
126 #if defined(CONFIG_MPC8360)
129 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
135 #if defined(CONFIG_MPC837X)
139 #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
143 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
146 clkin_div
= ((im
->clk
.spmr
& SPMR_CKID
) >> SPMR_CKID_SHIFT
);
148 if (im
->reset
.rcwh
& HRCWH_PCI_HOST
) {
149 #if defined(CONFIG_83XX_CLKIN)
150 pci_sync_in
= CONFIG_83XX_CLKIN
/ (1 + clkin_div
);
152 pci_sync_in
= 0xDEADBEEF;
155 #if defined(CONFIG_83XX_PCICLK)
156 pci_sync_in
= CONFIG_83XX_PCICLK
;
158 pci_sync_in
= 0xDEADBEEF;
162 spmf
= ((im
->reset
.rcwl
& HRCWL_SPMF
) >> HRCWL_SPMF_SHIFT
);
163 csb_clk
= pci_sync_in
* (1 + clkin_div
) * spmf
;
167 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
168 switch ((sccr
& SCCR_TSEC1CM
) >> SCCR_TSEC1CM_SHIFT
) {
176 tsec1_clk
= csb_clk
/ 2;
179 tsec1_clk
= csb_clk
/ 3;
182 /* unkown SCCR_TSEC1CM value */
186 switch ((sccr
& SCCR_USBDRCM
) >> SCCR_USBDRCM_SHIFT
) {
194 usbdr_clk
= csb_clk
/ 2;
197 usbdr_clk
= csb_clk
/ 3;
200 /* unkown SCCR_USBDRCM value */
205 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
206 switch ((sccr
& SCCR_TSEC2CM
) >> SCCR_TSEC2CM_SHIFT
) {
214 tsec2_clk
= csb_clk
/ 2;
217 tsec2_clk
= csb_clk
/ 3;
220 /* unkown SCCR_TSEC2CM value */
223 #elif defined(CONFIG_MPC8313)
224 tsec2_clk
= tsec1_clk
;
226 if (!(sccr
& SCCR_TSEC1ON
))
228 if (!(sccr
& SCCR_TSEC2ON
))
232 #if defined(CONFIG_MPC834X)
233 switch ((sccr
& SCCR_USBMPHCM
) >> SCCR_USBMPHCM_SHIFT
) {
238 usbmph_clk
= csb_clk
;
241 usbmph_clk
= csb_clk
/ 2;
244 usbmph_clk
= csb_clk
/ 3;
247 /* unkown SCCR_USBMPHCM value */
251 if (usbmph_clk
!= 0 && usbdr_clk
!= 0 && usbmph_clk
!= usbdr_clk
) {
252 /* if USB MPH clock is not disabled and
253 * USB DR clock is not disabled then
254 * USB MPH & USB DR must have the same rate
259 switch ((sccr
& SCCR_ENCCM
) >> SCCR_ENCCM_SHIFT
) {
267 enc_clk
= csb_clk
/ 2;
270 enc_clk
= csb_clk
/ 3;
273 /* unkown SCCR_ENCCM value */
277 #if defined(CONFIG_MPC837X)
278 switch ((sccr
& SCCR_SDHCCM
) >> SCCR_SDHCCM_SHIFT
) {
286 sdhc_clk
= csb_clk
/ 2;
289 sdhc_clk
= csb_clk
/ 3;
292 /* unkown SCCR_SDHCCM value */
296 #if defined(CONFIG_MPC8315)
297 switch ((sccr
& SCCR_TDMCM
) >> SCCR_TDMCM_SHIFT
) {
305 tdm_clk
= csb_clk
/ 2;
308 tdm_clk
= csb_clk
/ 3;
311 /* unkown SCCR_TDMCM value */
316 #if defined(CONFIG_MPC834X)
317 i2c1_clk
= tsec2_clk
;
318 #elif defined(CONFIG_MPC8360)
320 #elif defined(CONFIG_MPC832X)
322 #elif defined(CONFIG_MPC831X)
324 #elif defined(CONFIG_MPC837X)
327 #if !defined(CONFIG_MPC832X)
328 i2c2_clk
= csb_clk
; /* i2c-2 clk is equal to csb clk */
331 #if defined(CONFIG_MPC837X)
332 switch ((sccr
& SCCR_PCIEXP1CM
) >> SCCR_PCIEXP1CM_SHIFT
) {
337 pciexp1_clk
= csb_clk
;
340 pciexp1_clk
= csb_clk
/ 2;
343 pciexp1_clk
= csb_clk
/ 3;
346 /* unkown SCCR_PCIEXP1CM value */
350 switch ((sccr
& SCCR_PCIEXP2CM
) >> SCCR_PCIEXP2CM_SHIFT
) {
355 pciexp2_clk
= csb_clk
;
358 pciexp2_clk
= csb_clk
/ 2;
361 pciexp2_clk
= csb_clk
/ 3;
364 /* unkown SCCR_PCIEXP2CM value */
369 #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
370 switch ((sccr
& SCCR_SATA1CM
) >> SCCR_SATA1CM_SHIFT
) {
378 sata_clk
= csb_clk
/ 2;
381 sata_clk
= csb_clk
/ 3;
384 /* unkown SCCR_SATACM value */
390 (1 + ((im
->reset
.rcwl
& HRCWL_LBIUCM
) >> HRCWL_LBIUCM_SHIFT
));
391 lcrr
= (im
->lbus
.lcrr
& LCRR_CLKDIV
) >> LCRR_CLKDIV_SHIFT
;
396 lclk_clk
= lbiu_clk
/ lcrr
;
404 (1 + ((im
->reset
.rcwl
& HRCWL_DDRCM
) >> HRCWL_DDRCM_SHIFT
));
405 corepll
= (im
->reset
.rcwl
& HRCWL_COREPLL
) >> HRCWL_COREPLL_SHIFT
;
406 #if defined(CONFIG_MPC8360)
407 mem_sec_clk
= csb_clk
* (1 +
408 ((im
->reset
.rcwl
& HRCWL_LBIUCM
) >> HRCWL_LBIUCM_SHIFT
));
411 corecnf_tab_index
= ((corepll
& 0x1F) << 2) | ((corepll
& 0x60) >> 5);
412 if (corecnf_tab_index
> (sizeof(corecnf_tab
) / sizeof(corecnf_t
))) {
413 /* corecnf_tab_index is too high, possibly worng value */
416 switch (corecnf_tab
[corecnf_tab_index
].core_csb_ratio
) {
423 core_clk
= (3 * csb_clk
) / 2;
426 core_clk
= 2 * csb_clk
;
429 core_clk
= (5 * csb_clk
) / 2;
432 core_clk
= 3 * csb_clk
;
435 /* unkown core to csb ratio */
439 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
440 qepmf
= (im
->reset
.rcwl
& HRCWL_CEPMF
) >> HRCWL_CEPMF_SHIFT
;
441 qepdf
= (im
->reset
.rcwl
& HRCWL_CEPDF
) >> HRCWL_CEPDF_SHIFT
;
442 qe_clk
= (pci_sync_in
* qepmf
) / (1 + qepdf
);
443 brg_clk
= qe_clk
/ 2;
446 gd
->csb_clk
= csb_clk
;
447 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
448 gd
->tsec1_clk
= tsec1_clk
;
449 gd
->tsec2_clk
= tsec2_clk
;
450 gd
->usbdr_clk
= usbdr_clk
;
452 #if defined(CONFIG_MPC834X)
453 gd
->usbmph_clk
= usbmph_clk
;
455 #if defined(CONFIG_MPC8315)
456 gd
->tdm_clk
= tdm_clk
;
458 #if defined(CONFIG_MPC837X)
459 gd
->sdhc_clk
= sdhc_clk
;
461 gd
->core_clk
= core_clk
;
462 gd
->i2c1_clk
= i2c1_clk
;
463 #if !defined(CONFIG_MPC832X)
464 gd
->i2c2_clk
= i2c2_clk
;
466 gd
->enc_clk
= enc_clk
;
467 gd
->lbiu_clk
= lbiu_clk
;
468 gd
->lclk_clk
= lclk_clk
;
469 gd
->mem_clk
= mem_clk
;
470 #if defined(CONFIG_MPC8360)
471 gd
->mem_sec_clk
= mem_sec_clk
;
473 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
475 gd
->brg_clk
= brg_clk
;
477 #if defined(CONFIG_MPC837X)
478 gd
->pciexp1_clk
= pciexp1_clk
;
479 gd
->pciexp2_clk
= pciexp2_clk
;
481 #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
482 gd
->sata_clk
= sata_clk
;
484 gd
->pci_clk
= pci_sync_in
;
485 gd
->cpu_clk
= gd
->core_clk
;
486 gd
->bus_clk
= gd
->csb_clk
;
491 /********************************************
493 * return system bus freq in Hz
494 *********************************************/
495 ulong
get_bus_freq(ulong dummy
)
500 int do_clocks (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
502 printf("Clock configuration:\n");
503 printf(" Core: %4d MHz\n", gd
->core_clk
/ 1000000);
504 printf(" Coherent System Bus: %4d MHz\n", gd
->csb_clk
/ 1000000);
505 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
506 printf(" QE: %4d MHz\n", gd
->qe_clk
/ 1000000);
507 printf(" BRG: %4d MHz\n", gd
->brg_clk
/ 1000000);
509 printf(" Local Bus Controller:%4d MHz\n", gd
->lbiu_clk
/ 1000000);
510 printf(" Local Bus: %4d MHz\n", gd
->lclk_clk
/ 1000000);
511 printf(" DDR: %4d MHz\n", gd
->mem_clk
/ 1000000);
512 #if defined(CONFIG_MPC8360)
513 printf(" DDR Secondary: %4d MHz\n", gd
->mem_sec_clk
/ 1000000);
515 printf(" SEC: %4d MHz\n", gd
->enc_clk
/ 1000000);
516 printf(" I2C1: %4d MHz\n", gd
->i2c1_clk
/ 1000000);
517 #if !defined(CONFIG_MPC832X)
518 printf(" I2C2: %4d MHz\n", gd
->i2c2_clk
/ 1000000);
520 #if defined(CONFIG_MPC8315)
521 printf(" TDM: %4d MHz\n", gd
->tdm_clk
/ 1000000);
523 #if defined(CONFIG_MPC837X)
524 printf(" SDHC: %4d MHz\n", gd
->sdhc_clk
/ 1000000);
526 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
527 printf(" TSEC1: %4d MHz\n", gd
->tsec1_clk
/ 1000000);
528 printf(" TSEC2: %4d MHz\n", gd
->tsec2_clk
/ 1000000);
529 printf(" USB DR: %4d MHz\n", gd
->usbdr_clk
/ 1000000);
531 #if defined(CONFIG_MPC834X)
532 printf(" USB MPH: %4d MHz\n", gd
->usbmph_clk
/ 1000000);
534 #if defined(CONFIG_MPC837X)
535 printf(" PCIEXP1: %4d MHz\n", gd
->pciexp1_clk
/ 1000000);
536 printf(" PCIEXP2: %4d MHz\n", gd
->pciexp2_clk
/ 1000000);
538 #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
539 printf(" SATA: %4d MHz\n", gd
->sata_clk
/ 1000000);
544 U_BOOT_CMD(clocks
, 1, 0, do_clocks
,
545 "clocks - print clock configuration\n",