drivers/net/rtl8139.c

   1 /*
   2  * rtl8139.c : U-Boot driver for the RealTek RTL8139
   3  *
   4  * Masami Komiya (mkomiya@sonare.it)
   5  *
   6  * Most part is taken from rtl8139.c of etherboot
   7  *
   8  */
   9
  10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
  11
  12   ported from the linux driver written by Donald Becker
  13   by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
  14
  15   This software may be used and distributed according to the terms
  16   of the GNU Public License, incorporated herein by reference.
  17
  18   changes to the original driver:
  19   - removed support for interrupts, switching to polling mode (yuck!)
  20   - removed support for the 8129 chip (external MII)
  21
  22 */
  23
  24 /*********************************************************************/
  25 /* Revision History                                                  */
  26 /*********************************************************************/
  27
  28 /*
  29   28 Dec 2002   ken_yap@users.sourceforge.net (Ken Yap)
  30      Put in virt_to_bus calls to allow Etherboot relocation.
  31
  32   06 Apr 2001   ken_yap@users.sourceforge.net (Ken Yap)
  33      Following email from Hyun-Joon Cha, added a disable routine, otherwise
  34      NIC remains live and can crash the kernel later.
  35
  36   4 Feb 2000    espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
  37      Shuffled things around, removed the leftovers from the 8129 support
  38      that was in the Linux driver and added a bit more 8139 definitions.
  39      Moved the 8K receive buffer to a fixed, available address outside the
  40      0x98000-0x9ffff range.  This is a bit of a hack, but currently the only
  41      way to make room for the Etherboot features that need substantial amounts
  42      of code like the ANSI console support.  Currently the buffer is just below
  43      0x10000, so this even conforms to the tagged boot image specification,
  44      which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000.  My
  45      interpretation of this "reserved" is that Etherboot may do whatever it
  46      likes, as long as its environment is kept intact (like the BIOS
  47      variables).  Hopefully fixed rtl_poll() once and for all.  The symptoms
  48      were that if Etherboot was left at the boot menu for several minutes, the
  49      first eth_poll failed.  Seems like I am the only person who does this.
  50      First of all I fixed the debugging code and then set out for a long bug
  51      hunting session.  It took me about a week full time work - poking around
  52      various places in the driver, reading Don Becker's and Jeff Garzik's Linux
  53      driver and even the FreeBSD driver (what a piece of crap!) - and
  54      eventually spotted the nasty thing: the transmit routine was acknowledging
  55      each and every interrupt pending, including the RxOverrun and RxFIFIOver
  56      interrupts.  This confused the RTL8139 thoroughly.  It destroyed the
  57      Rx ring contents by dumping the 2K FIFO contents right where we wanted to
  58      get the next packet.  Oh well, what fun.
  59
  60   18 Jan 2000   mdc@thinguin.org (Marty Connor)
  61      Drastically simplified error handling.  Basically, if any error
  62      in transmission or reception occurs, the card is reset.
  63      Also, pointed all transmit descriptors to the same buffer to
  64      save buffer space.  This should decrease driver size and avoid
  65      corruption because of exceeding 32K during runtime.
  66
  67   28 Jul 1999   (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
  68      rtl_poll was quite broken: it used the RxOK interrupt flag instead
  69      of the RxBufferEmpty flag which often resulted in very bad
  70      transmission performace - below 1kBytes/s.
  71
  72 */
  73
  74 #include <common.h>
  75 #include <malloc.h>
  76 #include <net.h>
  77 #include <asm/io.h>
  78 #include <pci.h>
  79
  80 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
  81         defined(CONFIG_RTL8139)
  82
  83 #define RTL_TIMEOUT     100000
  84
  85 #define ETH_FRAME_LEN           1514
  86 #define ETH_ALEN                6
  87 #define ETH_ZLEN                60
  88
  89 /* PCI Tuning Parameters
  90    Threshold is bytes transferred to chip before transmission starts. */
  91 #define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */
  92 #define RX_FIFO_THRESH  4       /* Rx buffer level before first PCI xfer.  */
  93 #define RX_DMA_BURST    4       /* Maximum PCI burst, '4' is 256 bytes */
  94 #define TX_DMA_BURST    4       /* Calculate as 16<<val. */
  95 #define NUM_TX_DESC     4       /* Number of Tx descriptor registers. */
  96 #define TX_BUF_SIZE     ETH_FRAME_LEN   /* FCS is added by the chip */
  97 #define RX_BUF_LEN_IDX 0        /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
  98 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
  99
 100 #undef DEBUG_TX
 101 #undef DEBUG_RX
 102
 103 #define currticks()     get_timer(0)
 104 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)dev->priv, a)
 105 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)dev->priv, a)
 106
 107 /* Symbolic offsets to registers. */
 108 enum RTL8139_registers {
 109         MAC0=0,                 /* Ethernet hardware address. */
 110         MAR0=8,                 /* Multicast filter. */
 111         TxStatus0=0x10,         /* Transmit status (four 32bit registers). */
 112         TxAddr0=0x20,           /* Tx descriptors (also four 32bit). */
 113         RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
 114         ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
 115         IntrMask=0x3C, IntrStatus=0x3E,
 116         TxConfig=0x40, RxConfig=0x44,
 117         Timer=0x48,             /* general-purpose counter. */
 118         RxMissed=0x4C,          /* 24 bits valid, write clears. */
 119         Cfg9346=0x50, Config0=0x51, Config1=0x52,
 120         TimerIntrReg=0x54,      /* intr if gp counter reaches this value */
 121         MediaStatus=0x58,
 122         Config3=0x59,
 123         MultiIntr=0x5C,
 124         RevisionID=0x5E,        /* revision of the RTL8139 chip */
 125         TxSummary=0x60,
 126         MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
 127         NWayExpansion=0x6A,
 128         DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
 129         NWayTestReg=0x70,
 130         RxCnt=0x72,             /* packet received counter */
 131         CSCR=0x74,              /* chip status and configuration register */
 132         PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,   /* undocumented */
 133         /* from 0x84 onwards are a number of power management/wakeup frame
 134          * definitions we will probably never need to know about.  */
 135 };
 136
 137 enum ChipCmdBits {
 138         CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
 139
 140 /* Interrupt register bits, using my own meaningful names. */
 141 enum IntrStatusBits {
 142         PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
 143         RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
 144         TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
 145 };
 146 enum TxStatusBits {
 147         TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
 148         TxOutOfWindow=0x20000000, TxAborted=0x40000000,
 149         TxCarrierLost=0x80000000,
 150 };
 151 enum RxStatusBits {
 152         RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
 153         RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
 154         RxBadAlign=0x0002, RxStatusOK=0x0001,
 155 };
 156
 157 enum MediaStatusBits {
 158         MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
 159         MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
 160 };
 161
 162 enum MIIBMCRBits {
 163         BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
 164         BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
 165 };
 166
 167 enum CSCRBits {
 168         CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
 169         CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
 170         CSCR_LinkDownCmd=0x0f3c0,
 171 };
 172
 173 /* Bits in RxConfig. */
 174 enum rx_mode_bits {
 175         RxCfgWrap=0x80,
 176         AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
 177         AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
 178 };
 179
 180 static int ioaddr;
 181 static unsigned int cur_rx,cur_tx;
 182
 183 /* The RTL8139 can only transmit from a contiguous, aligned memory block.  */
 184 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
 185 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
 186
 187 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
 188 static int read_eeprom(int location, int addr_len);
 189 static void rtl_reset(struct eth_device *dev);
 190 static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
 191 static int rtl_poll(struct eth_device *dev);
 192 static void rtl_disable(struct eth_device *dev);
 193 #ifdef CONFIG_MCAST_TFTP/*  This driver already accepts all b/mcast */
 194 static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
 195 {
 196         return (0);
 197 }
 198 #endif
 199
 200 static struct pci_device_id supported[] = {
 201        {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
 202        {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
 203        {}
 204 };
 205
 206 int rtl8139_initialize(bd_t *bis)
 207 {
 208         pci_dev_t devno;
 209         int card_number = 0;
 210         struct eth_device *dev;
 211         u32 iobase;
 212         int idx=0;
 213
 214         while(1){
 215                 /* Find RTL8139 */
 216                 if ((devno = pci_find_devices(supported, idx++)) < 0)
 217                         break;
 218
 219                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
 220                 iobase &= ~0xf;
 221
 222                 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
 223
 224                 dev = (struct eth_device *)malloc(sizeof *dev);
 225
 226                 sprintf (dev->name, "RTL8139#%d", card_number);
 227
 228                 dev->priv = (void *) devno;
 229                 dev->iobase = (int)bus_to_phys(iobase);
 230                 dev->init = rtl8139_probe;
 231                 dev->halt = rtl_disable;
 232                 dev->send = rtl_transmit;
 233                 dev->recv = rtl_poll;
 234 #ifdef CONFIG_MCAST_TFTP
 235                 dev->mcast = rtl_bcast_addr;
 236 #endif
 237
 238                 eth_register (dev);
 239
 240                 card_number++;
 241
 242                 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
 243
 244                 udelay (10 * 1000);
 245         }
 246
 247         return card_number;
 248 }
 249
 250 static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
 251 {
 252         int i;
 253         int speed10, fullduplex;
 254         int addr_len;
 255         unsigned short *ap = (unsigned short *)dev->enetaddr;
 256
 257         ioaddr = dev->iobase;
 258
 259         /* Bring the chip out of low-power mode. */
 260         outb(0x00, ioaddr + Config1);
 261
 262         addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
 263         for (i = 0; i < 3; i++)
 264                 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
 265
 266         speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
 267         fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
 268
 269         rtl_reset(dev);
 270
 271         if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
 272                 printf("Cable not connected or other link failure\n");
 273                 return -1 ;
 274         }
 275
 276         return 0;
 277 }
 278
 279 /* Serial EEPROM section. */
 280
 281 /*  EEPROM_Ctrl bits. */
 282 #define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
 283 #define EE_CS           0x08    /* EEPROM chip select. */
 284 #define EE_DATA_WRITE   0x02    /* EEPROM chip data in. */
 285 #define EE_WRITE_0      0x00
 286 #define EE_WRITE_1      0x02
 287 #define EE_DATA_READ    0x01    /* EEPROM chip data out. */
 288 #define EE_ENB          (0x80 | EE_CS)
 289
 290 /*
 291         Delay between EEPROM clock transitions.
 292         No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
 293 */
 294
 295 #define eeprom_delay()  inl(ee_addr)
 296
 297 /* The EEPROM commands include the alway-set leading bit. */
 298 #define EE_WRITE_CMD    (5)
 299 #define EE_READ_CMD     (6)
 300 #define EE_ERASE_CMD    (7)
 301
 302 static int read_eeprom(int location, int addr_len)
 303 {
 304         int i;
 305         unsigned int retval = 0;
 306         long ee_addr = ioaddr + Cfg9346;
 307         int read_cmd = location | (EE_READ_CMD << addr_len);
 308
 309         outb(EE_ENB & ~EE_CS, ee_addr);
 310         outb(EE_ENB, ee_addr);
 311         eeprom_delay();
 312
 313         /* Shift the read command bits out. */
 314         for (i = 4 + addr_len; i >= 0; i--) {
 315                 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 316                 outb(EE_ENB | dataval, ee_addr);
 317                 eeprom_delay();
 318                 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
 319                 eeprom_delay();
 320         }
 321         outb(EE_ENB, ee_addr);
 322         eeprom_delay();
 323
 324         for (i = 16; i > 0; i--) {
 325                 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
 326                 eeprom_delay();
 327                 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
 328                 outb(EE_ENB, ee_addr);
 329                 eeprom_delay();
 330         }
 331
 332         /* Terminate the EEPROM access. */
 333         outb(~EE_CS, ee_addr);
 334         eeprom_delay();
 335         return retval;
 336 }
 337
 338 static const unsigned int rtl8139_rx_config =
 339         (RX_BUF_LEN_IDX << 11) |
 340         (RX_FIFO_THRESH << 13) |
 341         (RX_DMA_BURST << 8);
 342
 343 static void set_rx_mode(struct eth_device *dev) {
 344         unsigned int mc_filter[2];
 345         int rx_mode;
 346         /* !IFF_PROMISC */
 347         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
 348         mc_filter[1] = mc_filter[0] = 0xffffffff;
 349
 350         outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
 351
 352         outl(mc_filter[0], ioaddr + MAR0 + 0);
 353         outl(mc_filter[1], ioaddr + MAR0 + 4);
 354 }
 355
 356 static void rtl_reset(struct eth_device *dev)
 357 {
 358         int i;
 359
 360         outb(CmdReset, ioaddr + ChipCmd);
 361
 362         cur_rx = 0;
 363         cur_tx = 0;
 364
 365         /* Give the chip 10ms to finish the reset. */
 366         for (i=0; i<100; ++i){
 367                 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
 368                 udelay (100); /* wait 100us */
 369         }
 370
 371
 372         for (i = 0; i < ETH_ALEN; i++)
 373                 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
 374
 375         /* Must enable Tx/Rx before setting transfer thresholds! */
 376         outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
 377         outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
 378                 ioaddr + RxConfig);             /* accept no frames yet!  */
 379         outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
 380
 381         /* The Linux driver changes Config1 here to use a different LED pattern
 382          * for half duplex or full/autodetect duplex (for full/autodetect, the
 383          * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
 384          * TX/RX, Link100, Link10).  This is messy, because it doesn't match
 385          * the inscription on the mounting bracket.  It should not be changed
 386          * from the configuration EEPROM default, because the card manufacturer
 387          * should have set that to match the card.  */
 388
 389 #ifdef  DEBUG_RX
 390         printf("rx ring address is %X\n",(unsigned long)rx_ring);
 391 #endif
 392         flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
 393         outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
 394
 395         /* If we add multicast support, the MAR0 register would have to be
 396          * initialized to 0xffffffffffffffff (two 32 bit accesses).  Etherboot
 397          * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast.  */
 398
 399         outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
 400
 401         outl(rtl8139_rx_config, ioaddr + RxConfig);
 402
 403         /* Start the chip's Tx and Rx process. */
 404         outl(0, ioaddr + RxMissed);
 405
 406         /* set_rx_mode */
 407         set_rx_mode(dev);
 408
 409         /* Disable all known interrupts by setting the interrupt mask. */
 410         outw(0, ioaddr + IntrMask);
 411 }
 412
 413 static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
 414 {
 415         unsigned int status;
 416         unsigned long txstatus;
 417         unsigned int len = length;
 418         int i = 0;
 419
 420         ioaddr = dev->iobase;
 421
 422         memcpy((char *)tx_buffer, (char *)packet, (int)length);
 423
 424 #ifdef  DEBUG_TX
 425         printf("sending %d bytes\n", len);
 426 #endif
 427
 428         /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
 429          * bytes are sent automatically for the FCS, totalling to 64 bytes). */
 430         while (len < ETH_ZLEN) {
 431                 tx_buffer[len++] = '\0';
 432         }
 433
 434         flush_cache((unsigned long)tx_buffer, length);
 435         outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
 436         outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
 437                 ioaddr + TxStatus0 + cur_tx*4);
 438
 439         do {
 440                 status = inw(ioaddr + IntrStatus);
 441                 /* Only acknlowledge interrupt sources we can properly handle
 442                  * here - the RxOverflow/RxFIFOOver MUST be handled in the
 443                  * rtl_poll() function.  */
 444                 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
 445                 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
 446                 udelay(10);
 447         } while (i++ < RTL_TIMEOUT);
 448
 449         txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
 450
 451         if (status & TxOK) {
 452                 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
 453 #ifdef  DEBUG_TX
 454                 printf("tx done (%d ticks), status %hX txstatus %X\n",
 455                         to-currticks(), status, txstatus);
 456 #endif
 457                 return length;
 458         } else {
 459 #ifdef  DEBUG_TX
 460                 printf("tx timeout/error (%d usecs), status %hX txstatus %X\n",
 461                        10*i, status, txstatus);
 462 #endif
 463                 rtl_reset(dev);
 464
 465                 return 0;
 466         }
 467 }
 468
 469 static int rtl_poll(struct eth_device *dev)
 470 {
 471         unsigned int status;
 472         unsigned int ring_offs;
 473         unsigned int rx_size, rx_status;
 474         int length=0;
 475
 476         ioaddr = dev->iobase;
 477
 478         if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
 479                 return 0;
 480         }
 481
 482         status = inw(ioaddr + IntrStatus);
 483         /* See below for the rest of the interrupt acknowledges.  */
 484         outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
 485
 486 #ifdef  DEBUG_RX
 487         printf("rtl_poll: int %hX ", status);
 488 #endif
 489
 490         ring_offs = cur_rx % RX_BUF_LEN;
 491         /* ring_offs is guaranteed being 4-byte aligned */
 492         rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
 493         rx_size = rx_status >> 16;
 494         rx_status &= 0xffff;
 495
 496         if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
 497             (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
 498                 printf("rx error %hX\n", rx_status);
 499                 rtl_reset(dev); /* this clears all interrupts still pending */
 500                 return 0;
 501         }
 502
 503         /* Received a good packet */
 504         length = rx_size - 4;   /* no one cares about the FCS */
 505         if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
 506                 int semi_count = RX_BUF_LEN - ring_offs - 4;
 507                 unsigned char rxdata[RX_BUF_LEN];
 508
 509                 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
 510                 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
 511
 512                 NetReceive(rxdata, length);
 513 #ifdef  DEBUG_RX
 514                 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
 515 #endif
 516         } else {
 517                 NetReceive(rx_ring + ring_offs + 4, length);
 518 #ifdef  DEBUG_RX
 519                 printf("rx packet %d bytes", rx_size-4);
 520 #endif
 521         }
 522         flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
 523
 524         cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
 525         outw(cur_rx - 16, ioaddr + RxBufPtr);
 526         /* See RTL8139 Programming Guide V0.1 for the official handling of
 527          * Rx overflow situations.  The document itself contains basically no
 528          * usable information, except for a few exception handling rules.  */
 529         outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
 530         return length;
 531 }
 532
 533 static void rtl_disable(struct eth_device *dev)
 534 {
 535         int i;
 536
 537         ioaddr = dev->iobase;
 538
 539         /* reset the chip */
 540         outb(CmdReset, ioaddr + ChipCmd);
 541
 542         /* Give the chip 10ms to finish the reset. */
 543         for (i=0; i<100; ++i){
 544                 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
 545                 udelay (100); /* wait 100us */
 546         }
 547 }
 548 #endif