board/freescale/mpc8313erdb/sdram.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
   3  *
   4  * Authors: Nick.Spence@freescale.com
   5  *          Wilson.Lo@freescale.com
   6  *          scottwood@freescale.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc83xx.h>
  29 #include <spd_sdram.h>
  30
  31 #include <asm/bitops.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/processor.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #ifndef CFG_8313ERDB_BROKEN_PMC
  39 static void resume_from_sleep(void)
  40 {
  41         u32 magic = *(u32 *)0;
  42
  43         typedef void (*func_t)(void);
  44         func_t resume = *(func_t *)4;
  45
  46         if (magic == 0xf5153ae5)
  47                 resume();
  48
  49         gd->flags &= ~GD_FLG_SILENT;
  50         puts("\nResume from sleep failed: bad magic word\n");
  51 }
  52 #endif
  53
  54 /* Fixed sdram init -- doesn't use serial presence detect.
  55  *
  56  * This is useful for faster booting in configs where the RAM is unlikely
  57  * to be changed, or for things like NAND booting where space is tight.
  58  */
  59 static long fixed_sdram(void)
  60 {
  61         volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
  62         u32 msize = CFG_DDR_SIZE * 1024 * 1024;
  63         u32 msize_log2 = __ilog2(msize);
  64
  65         im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
  66         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  67         im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
  68
  69         /*
  70          * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  71          * or the DDR2 controller may fail to initialize correctly.
  72          */
  73         udelay(50000);
  74
  75         im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
  76         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
  77
  78         /* Currently we use only one CS, so disable the other bank. */
  79         im->ddr.cs_config[1] = 0;
  80
  81         im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
  82         im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
  83         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
  84         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
  85         im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
  86
  87 #ifndef CFG_8313ERDB_BROKEN_PMC
  88         if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  89                 im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI;
  90         else
  91 #endif
  92                 im->ddr.sdram_cfg = CFG_SDRAM_CFG;
  93
  94         im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2;
  95         im->ddr.sdram_mode = CFG_DDR_MODE;
  96         im->ddr.sdram_mode2 = CFG_DDR_MODE_2;
  97
  98         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
  99         sync();
 100
 101         /* enable DDR controller */
 102         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 103
 104         return msize;
 105 }
 106
 107 long int initdram(int board_type)
 108 {
 109         volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 110         volatile lbus83xx_t *lbc = &im->lbus;
 111         u32 msize;
 112
 113         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 114                 return -1;
 115
 116         /* DDR SDRAM - Main SODIMM */
 117         msize = fixed_sdram();
 118
 119         /* Local Bus setup lbcr and mrtpr */
 120         lbc->lbcr = CFG_LBC_LBCR;
 121         lbc->mrtpr = CFG_LBC_MRTPR;
 122         sync();
 123
 124 #ifndef CFG_8313ERDB_BROKEN_PMC
 125         if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 126                 resume_from_sleep();
 127 #endif
 128
 129         /* return total bus SDRAM size(bytes)  -- DDR */
 130         return msize;
 131 }