include/asm-mips/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2000 FSMLabs, Inc.
  10  */
  11 #ifndef _ASM_IO_H
  12 #define _ASM_IO_H
  13
  14 #include <linux/config.h>
  15 #if 0
  16 #include <linux/pagemap.h>
  17 #endif
  18 #include <asm/addrspace.h>
  19 #include <asm/byteorder.h>
  20
  21 /*
  22  * Slowdown I/O port space accesses for antique hardware.
  23  */
  24 #undef CONF_SLOWDOWN_IO
  25
  26 /*
  27  * Sane hardware offers swapping of I/O space accesses in hardware; less
  28  * sane hardware forces software to fiddle with this ...
  29  */
  30 #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
  31
  32 #define __ioswab8(x) (x)
  33 #define __ioswab16(x) swab16(x)
  34 #define __ioswab32(x) swab32(x)
  35
  36 #else
  37
  38 #define __ioswab8(x) (x)
  39 #define __ioswab16(x) (x)
  40 #define __ioswab32(x) (x)
  41
  42 #endif
  43
  44 /*
  45  * This file contains the definitions for the MIPS counterpart of the
  46  * x86 in/out instructions. This heap of macros and C results in much
  47  * better code than the approach of doing it in plain C.  The macros
  48  * result in code that is to fast for certain hardware.  On the other
  49  * side the performance of the string functions should be improved for
  50  * sake of certain devices like EIDE disks that do highspeed polled I/O.
  51  *
  52  *   Ralf
  53  *
  54  * This file contains the definitions for the x86 IO instructions
  55  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
  56  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
  57  * versions of the single-IO instructions (inb_p/inw_p/..).
  58  *
  59  * This file is not meant to be obfuscating: it's just complicated
  60  * to (a) handle it all in a way that makes gcc able to optimize it
  61  * as well as possible and (b) trying to avoid writing the same thing
  62  * over and over again with slight variations and possibly making a
  63  * mistake somewhere.
  64  */
  65
  66 /*
  67  * On MIPS I/O ports are memory mapped, so we access them using normal
  68  * load/store instructions. mips_io_port_base is the virtual address to
  69  * which all ports are being mapped.  For sake of efficiency some code
  70  * assumes that this is an address that can be loaded with a single lui
  71  * instruction, so the lower 16 bits must be zero.  Should be true on
  72  * on any sane architecture; generic code does not use this assumption.
  73  */
  74 extern const unsigned long mips_io_port_base;
  75
  76 /*
  77  * Gcc will generate code to load the value of mips_io_port_base after each
  78  * function call which may be fairly wasteful in some cases.  So we don't
  79  * play quite by the book.  We tell gcc mips_io_port_base is a long variable
  80  * which solves the code generation issue.  Now we need to violate the
  81  * aliasing rules a little to make initialization possible and finally we
  82  * will need the barrier() to fight side effects of the aliasing chat.
  83  * This trickery will eventually collapse under gcc's optimizer.  Oh well.
  84  */
  85 static inline void set_io_port_base(unsigned long base)
  86 {
  87         * (unsigned long *) &mips_io_port_base = base;
  88 }
  89
  90 /*
  91  * Thanks to James van Artsdalen for a better timing-fix than
  92  * the two short jumps: using outb's to a nonexistent port seems
  93  * to guarantee better timings even on fast machines.
  94  *
  95  * On the other hand, I'd like to be sure of a non-existent port:
  96  * I feel a bit unsafe about using 0x80 (should be safe, though)
  97  *
  98  *              Linus
  99  *
 100  */
 101
 102 #define __SLOW_DOWN_IO \
 103         __asm__ __volatile__( \
 104                 "sb\t$0,0x80(%0)" \
 105                 : : "r" (mips_io_port_base));
 106
 107 #ifdef CONF_SLOWDOWN_IO
 108 #ifdef REALLY_SLOW_IO
 109 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
 110 #else
 111 #define SLOW_DOWN_IO __SLOW_DOWN_IO
 112 #endif
 113 #else
 114 #define SLOW_DOWN_IO
 115 #endif
 116
 117 /*
 118  * Change virtual addresses to physical addresses and vv.
 119  * These are trivial on the 1:1 Linux/MIPS mapping
 120  */
 121 extern inline unsigned long virt_to_phys(volatile void * address)
 122 {
 123         return PHYSADDR(address);
 124 }
 125
 126 extern inline void * phys_to_virt(unsigned long address)
 127 {
 128         return (void *)KSEG0ADDR(address);
 129 }
 130
 131 /*
 132  * IO bus memory addresses are also 1:1 with the physical address
 133  */
 134 extern inline unsigned long virt_to_bus(volatile void * address)
 135 {
 136         return PHYSADDR(address);
 137 }
 138
 139 extern inline void * bus_to_virt(unsigned long address)
 140 {
 141         return (void *)KSEG0ADDR(address);
 142 }
 143
 144 /*
 145  * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
 146  * for the processor.
 147  */
 148 extern unsigned long isa_slot_offset;
 149
 150 extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
 151
 152 #if 0
 153 extern inline void *ioremap(unsigned long offset, unsigned long size)
 154 {
 155         return __ioremap(offset, size, _CACHE_UNCACHED);
 156 }
 157
 158 extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
 159 {
 160         return __ioremap(offset, size, _CACHE_UNCACHED);
 161 }
 162
 163 extern void iounmap(void *addr);
 164 #endif
 165
 166 /*
 167  * XXX We need system specific versions of these to handle EISA address bits
 168  * 24-31 on SNI.
 169  * XXX more SNI hacks.
 170  */
 171 #define readb(addr) (*(volatile unsigned char *)(addr))
 172 #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
 173 #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
 174 #define __raw_readb readb
 175 #define __raw_readw readw
 176 #define __raw_readl readl
 177
 178 #define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
 179 #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b))
 180 #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b))
 181 #define __raw_writeb writeb
 182 #define __raw_writew writew
 183 #define __raw_writel writel
 184
 185 #define memset_io(a,b,c)        memset((void *)(a),(b),(c))
 186 #define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
 187 #define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
 188
 189 /* END SNI HACKS ... */
 190
 191 /*
 192  * ISA space is 'always mapped' on currently supported MIPS systems, no need
 193  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
 194  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 195  * are physical addresses. The following constant pointer can be
 196  * used as the IO-area pointer (it can be iounmapped as well, so the
 197  * analogy with PCI is quite large):
 198  */
 199 #define __ISA_IO_base ((char *)(PAGE_OFFSET))
 200
 201 #define isa_readb(a) readb(a)
 202 #define isa_readw(a) readw(a)
 203 #define isa_readl(a) readl(a)
 204 #define isa_writeb(b,a) writeb(b,a)
 205 #define isa_writew(w,a) writew(w,a)
 206 #define isa_writel(l,a) writel(l,a)
 207
 208 #define isa_memset_io(a,b,c)     memset_io((a),(b),(c))
 209 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
 210 #define isa_memcpy_toio(a,b,c)   memcpy_toio((a),(b),(c))
 211
 212 /*
 213  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
 214  * just copy it. The net code will then do the checksum later.
 215  */
 216 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
 217 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
 218
 219 static inline int check_signature(unsigned long io_addr,
 220                                   const unsigned char *signature, int length)
 221 {
 222         int retval = 0;
 223         do {
 224                 if (readb(io_addr) != *signature)
 225                         goto out;
 226                 io_addr++;
 227                 signature++;
 228                 length--;
 229         } while (length);
 230         retval = 1;
 231 out:
 232         return retval;
 233 }
 234 #define isa_check_signature(io, s, l) check_signature(i,s,l)
 235
 236 /*
 237  * Talk about misusing macros..
 238  */
 239
 240 #define __OUT1(s) \
 241 extern inline void __out##s(unsigned int value, unsigned int port) {
 242
 243 #define __OUT2(m) \
 244 __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
 245
 246 #define __OUT(m,s,w) \
 247 __OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
 248 __OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
 249 __OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
 250         SLOW_DOWN_IO; } \
 251 __OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
 252         SLOW_DOWN_IO; }
 253
 254 #define __IN1(t,s) \
 255 extern __inline__ t __in##s(unsigned int port) { t _v;
 256
 257 /*
 258  * Required nops will be inserted by the assembler
 259  */
 260 #define __IN2(m) \
 261 __asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
 262
 263 #define __IN(t,m,s,w) \
 264 __IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
 265 __IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
 266 __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
 267 __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
 268
 269 #define __INS1(s) \
 270 extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
 271
 272 #define __INS2(m) \
 273 if (count) \
 274 __asm__ __volatile__ ( \
 275         ".set\tnoreorder\n\t" \
 276         ".set\tnoat\n" \
 277         "1:\tl" #m "\t$1,%4(%5)\n\t" \
 278         "subu\t%1,1\n\t" \
 279         "s" #m "\t$1,(%0)\n\t" \
 280         "bne\t$0,%1,1b\n\t" \
 281         "addiu\t%0,%6\n\t" \
 282         ".set\tat\n\t" \
 283         ".set\treorder"
 284
 285 #define __INS(m,s,i) \
 286 __INS1(s) __INS2(m) \
 287         : "=r" (addr), "=r" (count) \
 288         : "0" (addr), "1" (count), "i" (0), \
 289           "r" (mips_io_port_base+port), "I" (i) \
 290         : "$1");} \
 291 __INS1(s##c) __INS2(m) \
 292         : "=r" (addr), "=r" (count) \
 293         : "0" (addr), "1" (count), "ir" (port), \
 294           "r" (mips_io_port_base), "I" (i) \
 295         : "$1");}
 296
 297 #define __OUTS1(s) \
 298 extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
 299
 300 #define __OUTS2(m) \
 301 if (count) \
 302 __asm__ __volatile__ ( \
 303         ".set\tnoreorder\n\t" \
 304         ".set\tnoat\n" \
 305         "1:\tl" #m "\t$1,(%0)\n\t" \
 306         "subu\t%1,1\n\t" \
 307         "s" #m "\t$1,%4(%5)\n\t" \
 308         "bne\t$0,%1,1b\n\t" \
 309         "addiu\t%0,%6\n\t" \
 310         ".set\tat\n\t" \
 311         ".set\treorder"
 312
 313 #define __OUTS(m,s,i) \
 314 __OUTS1(s) __OUTS2(m) \
 315         : "=r" (addr), "=r" (count) \
 316         : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
 317         : "$1");} \
 318 __OUTS1(s##c) __OUTS2(m) \
 319         : "=r" (addr), "=r" (count) \
 320         : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
 321         : "$1");}
 322
 323 __IN(unsigned char,b,b,8)
 324 __IN(unsigned short,h,w,16)
 325 __IN(unsigned int,w,l,32)
 326
 327 __OUT(b,b,8)
 328 __OUT(h,w,16)
 329 __OUT(w,l,32)
 330
 331 __INS(b,b,1)
 332 __INS(h,w,2)
 333 __INS(w,l,4)
 334
 335 __OUTS(b,b,1)
 336 __OUTS(h,w,2)
 337 __OUTS(w,l,4)
 338
 339
 340 /*
 341  * Note that due to the way __builtin_constant_p() works, you
 342  *  - can't use it inside an inline function (it will never be true)
 343  *  - you don't have to worry about side effects within the __builtin..
 344  */
 345 #define outb(val,port) \
 346 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 347         __outbc((val),(port)) : \
 348         __outb((val),(port)))
 349
 350 #define inb(port) \
 351 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 352         __inbc(port) : \
 353         __inb(port))
 354
 355 #define outb_p(val,port) \
 356 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 357         __outbc_p((val),(port)) : \
 358         __outb_p((val),(port)))
 359
 360 #define inb_p(port) \
 361 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 362         __inbc_p(port) : \
 363         __inb_p(port))
 364
 365 #define outw(val,port) \
 366 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 367         __outwc((val),(port)) : \
 368         __outw((val),(port)))
 369
 370 #define inw(port) \
 371 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 372         __inwc(port) : \
 373         __inw(port))
 374
 375 #define outw_p(val,port) \
 376 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 377         __outwc_p((val),(port)) : \
 378         __outw_p((val),(port)))
 379
 380 #define inw_p(port) \
 381 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 382         __inwc_p(port) : \
 383         __inw_p(port))
 384
 385 #define outl(val,port) \
 386 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 387         __outlc((val),(port)) : \
 388         __outl((val),(port)))
 389
 390 #define inl(port) \
 391 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 392         __inlc(port) : \
 393         __inl(port))
 394
 395 #define outl_p(val,port) \
 396 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 397         __outlc_p((val),(port)) : \
 398         __outl_p((val),(port)))
 399
 400 #define inl_p(port) \
 401 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 402         __inlc_p(port) : \
 403         __inl_p(port))
 404
 405
 406 #define outsb(port,addr,count) \
 407 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 408         __outsbc((port),(addr),(count)) : \
 409         __outsb ((port),(addr),(count)))
 410
 411 #define insb(port,addr,count) \
 412 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 413         __insbc((port),(addr),(count)) : \
 414         __insb((port),(addr),(count)))
 415
 416 #define outsw(port,addr,count) \
 417 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 418         __outswc((port),(addr),(count)) : \
 419         __outsw ((port),(addr),(count)))
 420
 421 #define insw(port,addr,count) \
 422 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 423         __inswc((port),(addr),(count)) : \
 424         __insw((port),(addr),(count)))
 425
 426 #define outsl(port,addr,count) \
 427 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 428         __outslc((port),(addr),(count)) : \
 429         __outsl ((port),(addr),(count)))
 430
 431 #define insl(port,addr,count) \
 432 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 433         __inslc((port),(addr),(count)) : \
 434         __insl((port),(addr),(count)))
 435
 436 #define IO_SPACE_LIMIT 0xffff
 437
 438 /*
 439  * The caches on some architectures aren't dma-coherent and have need to
 440  * handle this in software.  There are three types of operations that
 441  * can be applied to dma buffers.
 442  *
 443  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 444  *    writing the content of the caches back to memory, if necessary.
 445  *    The function also invalidates the affected part of the caches as
 446  *    necessary before DMA transfers from outside to memory.
 447  *  - dma_cache_wback(start, size) makes caches and coherent by
 448  *    writing the content of the caches back to memory, if necessary.
 449  *    The function also invalidates the affected part of the caches as
 450  *    necessary before DMA transfers from outside to memory.
 451  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 452  *    caches.  Dirty lines of the caches may be written back or simply
 453  *    be discarded.  This operation is necessary before dma operations
 454  *    to the memory.
 455  */
 456 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 457 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 458 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 459
 460 #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
 461 #define dma_cache_wback(start,size)     _dma_cache_wback(start,size)
 462 #define dma_cache_inv(start,size)       _dma_cache_inv(start,size)
 463
 464 static inline void sync(void)
 465 {
 466 }
 467
 468 /*
 469  * Given a physical address and a length, return a virtual address
 470  * that can be used to access the memory range with the caching
 471  * properties specified by "flags".
 472  */
 473 typedef unsigned long phys_addr_t;
 474
 475 #define MAP_NOCACHE     (0)
 476 #define MAP_WRCOMBINE   (0)
 477 #define MAP_WRBACK      (0)
 478 #define MAP_WRTHROUGH   (0)
 479
 480 static inline void *
 481 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 482 {
 483         return (void *)paddr;
 484 }
 485
 486 /*
 487  * Take down a mapping set up by map_physmem().
 488  */
 489 static inline void unmap_physmem(void *vaddr, unsigned long flags)
 490 {
 491
 492 }
 493
 494 #endif /* _ASM_IO_H */