include/configs/bamboo.h

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * bamboo.h - configuration for BAMBOO board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_BAMBOO           1       /* Board is BAMBOO              */
  34 #define CONFIG_440EP            1       /* Specific PPC440EP support    */
  35 #define CONFIG_440              1       /* ... PPC440 family            */
  36 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  37 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  38
  39 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  40
  41 /*
  42  * Please note that, if NAND support is enabled, the 2nd ethernet port
  43  * can't be used because of pin multiplexing. So, if you want to use the
  44  * 2nd ethernet port you have to "undef" the following define.
  45  */
  46 #define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
  47
  48 /*-----------------------------------------------------------------------
  49  * Base addresses -- Note these are effective addresses where the
  50  * actual resources get mapped (not physical addresses)
  51  *----------------------------------------------------------------------*/
  52 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  53 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
  54 #define CFG_MONITOR_BASE        TEXT_BASE
  55 #define CFG_SDRAM_BASE          0x00000000          /* _must_ be 0      */
  56 #define CFG_FLASH_BASE          0xfff00000          /* start of FLASH   */
  57 #define CFG_PCI_MEMBASE         0xa0000000          /* mapped pci memory*/
  58 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  59 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  60 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  61
  62 /*Don't change either of these*/
  63 #define CFG_PERIPHERAL_BASE     0xef600000          /* internal peripherals*/
  64 #define CFG_PCI_BASE            0xe0000000          /* internal PCI regs*/
  65 /*Don't change either of these*/
  66
  67 #define CFG_USB_DEVICE          0x50000000
  68 #define CFG_NVRAM_BASE_ADDR     0x80000000
  69 #define CFG_BOOT_BASE_ADDR      0xf0000000
  70 #define CFG_NAND_ADDR           0x90000000
  71 #define CFG_NAND2_ADDR          0x94000000
  72
  73 /*-----------------------------------------------------------------------
  74  * Initial RAM & stack pointer (placed in SDRAM)
  75  *----------------------------------------------------------------------*/
  76 #define CFG_INIT_RAM_DCACHE     1               /* d-cache as init ram  */
  77 #define CFG_INIT_RAM_ADDR       0x70000000      /* DCache       */
  78 #define CFG_INIT_RAM_END        (4 << 10)
  79 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data       */
  80 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  81 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  82
  83 /*-----------------------------------------------------------------------
  84  * Serial Port
  85  *----------------------------------------------------------------------*/
  86 #define CFG_EXT_SERIAL_CLOCK    11059200 /* use external 11.059MHz clk  */
  87 #define CONFIG_BAUDRATE         115200
  88 #define CONFIG_SERIAL_MULTI     1
  89 /* define this if you want console on UART1 */
  90 #undef CONFIG_UART1_CONSOLE
  91
  92 #define CFG_BAUDRATE_TABLE  \
  93     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  94
  95 /*-----------------------------------------------------------------------
  96  * NVRAM/RTC
  97  *
  98  * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
  99  * The DS1558 code assumes this condition
 100  *
 101  *----------------------------------------------------------------------*/
 102 #define CFG_NVRAM_SIZE          (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
 103 #define CONFIG_RTC_DS1556       1                        /* DS1556 RTC          */
 104
 105 /*-----------------------------------------------------------------------
 106  * Environment
 107  *----------------------------------------------------------------------*/
 108 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 109 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 110 #else
 111 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environment vars        */
 112 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
 113 #endif
 114
 115 /*-----------------------------------------------------------------------
 116  * FLASH related
 117  *----------------------------------------------------------------------*/
 118 #define CFG_MAX_FLASH_BANKS     3       /* number of banks                      */
 119 #define CFG_MAX_FLASH_SECT      256     /* sectors per device                   */
 120
 121 #undef  CFG_FLASH_CHECKSUM
 122 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 123 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 124
 125 #define CFG_FLASH_ADDR0         0x555
 126 #define CFG_FLASH_ADDR1         0x2aa
 127 #define CFG_FLASH_WORD_SIZE     unsigned char
 128
 129 #define CFG_FLASH_2ND_16BIT_DEV 1       /* bamboo has 8 and 16bit device        */
 130 #define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device    */
 131
 132 #ifdef CFG_ENV_IS_IN_FLASH
 133 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector          */
 134 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 135 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 136
 137 /* Address and size of Redundant Environment Sector     */
 138 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 139 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 140 #endif /* CFG_ENV_IS_IN_FLASH */
 141
 142 /*
 143  * IPL (Initial Program Loader, integrated inside CPU)
 144  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 145  *
 146  * SPL (Secondary Program Loader)
 147  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 148  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 149  * controller and the NAND controller so that the special U-Boot image can be
 150  * loaded from NAND to SDRAM.
 151  *
 152  * NUB (NAND U-Boot)
 153  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 154  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 155  *
 156  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 157  * set up. While still running from cache, I experienced problems accessing
 158  * the NAND controller. sr - 2006-08-25
 159  */
 160 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
 161 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
 162 #define CFG_NAND_BOOT_SPL_DST   0x00800000      /* Copy SPL here                */
 163 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
 164 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 165 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 166
 167 /*
 168  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 169  */
 170 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
 171 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
 172
 173 /*
 174  * Now the NAND chip has to be defined (no autodetection used!)
 175  */
 176 #define CFG_NAND_PAGE_SIZE      512             /* NAND chip page size          */
 177 #define CFG_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size         */
 178 #define CFG_NAND_PAGE_COUNT     32              /* NAND chip page count         */
 179 #define CFG_NAND_BAD_BLOCK_POS  5               /* Location of bad block marker */
 180 #define CFG_NAND_4_ADDR_CYCLE   1               /* Fourth addr used (>32MB)     */
 181
 182 #define CFG_NAND_ECCSIZE        256
 183 #define CFG_NAND_ECCBYTES       3
 184 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 185 #define CFG_NAND_OOBSIZE        16
 186 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 187 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 188
 189 #ifdef CFG_ENV_IS_IN_NAND
 190 /*
 191  * For NAND booting the environment is embedded in the U-Boot image. Please take
 192  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 193  */
 194 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 195 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 196 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 197 #endif
 198
 199 /*-----------------------------------------------------------------------
 200  * NAND FLASH
 201  *----------------------------------------------------------------------*/
 202 #define CFG_MAX_NAND_DEVICE     2
 203 #define NAND_MAX_CHIPS          CFG_MAX_NAND_DEVICE
 204 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 205 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
 206 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 207
 208 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 209 #define CFG_NAND_CS             1
 210 #else
 211 #define CFG_NAND_CS             0               /* NAND chip connected to CSx   */
 212 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 213 #define CFG_EBC_PB0AP           0x018003c0
 214 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1c000)
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * DDR SDRAM
 219  *----------------------------------------------------------------------------- */
 220 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 221 #undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 222 #define CFG_SIMULATE_SPD_EEPROM 0xff    /* simulate spd eeprom on this address  */
 223 #define SPD_EEPROM_ADDRESS      {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
 224 #define CFG_MBYTES_SDRAM        (64)    /* 64MB fixed size for early-sdram-init */
 225 #define CONFIG_PROG_SDRAM_TLB
 226 #undef  CFG_DRAM_TEST
 227
 228 /*-----------------------------------------------------------------------
 229  * I2C
 230  *----------------------------------------------------------------------*/
 231 #define CONFIG_HARD_I2C         1           /* I2C with hardware support        */
 232 #undef  CONFIG_SOFT_I2C                     /* I2C bit-banged           */
 233 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 234 #define CFG_I2C_SLAVE           0x7F
 235
 236 #define CFG_I2C_MULTI_EEPROMS
 237 #define CFG_I2C_EEPROM_ADDR     (0xa8>>1)
 238 #define CFG_I2C_EEPROM_ADDR_LEN 1
 239 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 240 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 241 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 242
 243 #ifdef CFG_ENV_IS_IN_EEPROM
 244 #define CFG_ENV_SIZE            0x200       /* Size of Environment vars */
 245 #define CFG_ENV_OFFSET          0x0
 246 #endif /* CFG_ENV_IS_IN_EEPROM */
 247
 248 #define CONFIG_PREBOOT  "echo;" \
 249         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 250         "echo"
 251
 252 #undef  CONFIG_BOOTARGS
 253
 254 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 255         "netdev=eth0\0"                                                 \
 256         "hostname=bamboo\0"                                             \
 257         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 258                 "nfsroot=${serverip}:${rootpath}\0"                     \
 259         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 260         "addip=setenv bootargs ${bootargs} "                            \
 261                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 262                 ":${hostname}:${netdev}:off panic=1\0"                  \
 263         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 264         "flash_nfs=run nfsargs addip addtty;"                           \
 265                 "bootm ${kernel_addr}\0"                                \
 266         "flash_self=run ramargs addip addtty;"                          \
 267                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 268         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 269                 "bootm\0"                                               \
 270         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 271         "bootfile=/tftpboot/bamboo/uImage\0"                            \
 272         "kernel_addr=fff00000\0"                                        \
 273         "ramdisk_addr=fff10000\0"                                       \
 274         "initrd_high=30000000\0"                                        \
 275         "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0"                \
 276         "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"   \
 277                 "cp.b 100000 fffa0000 60000;"                           \
 278                 "setenv filesize;saveenv\0"                             \
 279         "upd=run load update\0"                                         \
 280         ""
 281 #define CONFIG_BOOTCOMMAND      "run flash_self"
 282
 283 #if 0
 284 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 285 #else
 286 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 287 #endif
 288
 289 #define CONFIG_BAUDRATE         115200
 290
 291 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 292 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 293
 294 #define CONFIG_MII              1       /* MII PHY management           */
 295 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 296 #define CONFIG_PHY1_ADDR        1
 297
 298 #ifndef CONFIG_BAMBOO_NAND
 299 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 300 #endif /* CONFIG_BAMBOO_NAND */
 301
 302 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 303
 304 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 305 #define CONFIG_NET_MULTI        1       /* required for netconsole      */
 306
 307 /* Partitions */
 308 #define CONFIG_MAC_PARTITION
 309 #define CONFIG_DOS_PARTITION
 310 #define CONFIG_ISO_PARTITION
 311
 312 #ifdef CONFIG_440EP
 313 /* USB */
 314 #define CONFIG_USB_OHCI
 315 #define CONFIG_USB_STORAGE
 316
 317 /*Comment this out to enable USB 1.1 device*/
 318 #define USB_2_0_DEVICE
 319 #endif /*CONFIG_440EP*/
 320
 321
 322 /*
 323  * BOOTP options
 324  */
 325 #define CONFIG_BOOTP_BOOTFILESIZE
 326 #define CONFIG_BOOTP_BOOTPATH
 327 #define CONFIG_BOOTP_GATEWAY
 328 #define CONFIG_BOOTP_HOSTNAME
 329
 330
 331 /*
 332  * Command line configuration.
 333  */
 334 #include <config_cmd_default.h>
 335
 336
 337 #define CONFIG_CMD_ASKENV
 338 #define CONFIG_CMD_DATE
 339 #define CONFIG_CMD_DHCP
 340 #define CONFIG_CMD_DIAG
 341 #define CONFIG_CMD_ELF
 342 #define CONFIG_CMD_EEPROM
 343 #define CONFIG_CMD_I2C
 344 #define CONFIG_CMD_IRQ
 345 #define CONFIG_CMD_MII
 346 #define CONFIG_CMD_NET
 347 #define CONFIG_CMD_NFS
 348 #define CONFIG_CMD_PCI
 349 #define CONFIG_CMD_PING
 350 #define CONFIG_CMD_REGINFO
 351 #define CONFIG_CMD_SDRAM
 352 #define CONFIG_CMD_USB
 353 #define CONFIG_CMD_FAT
 354 #define CONFIG_CMD_EXT2
 355 #define CONFIG_CMD_SNTP
 356
 357 #ifdef CONFIG_BAMBOO_NAND
 358 #define CONFIG_CMD_NAND
 359 #endif
 360
 361
 362 #define CONFIG_SUPPORT_VFAT
 363
 364 /*
 365  * Miscellaneous configurable options
 366  */
 367 #define CFG_LONGHELP                    /* undef to save memory         */
 368 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 369 #if defined(CONFIG_CMD_KGDB)
 370 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 371 #else
 372 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 373 #endif
 374 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 375 #define CFG_MAXARGS             16      /* max number of command args   */
 376 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 377
 378 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 379 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 380
 381 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 382 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 383 #define CONFIG_LYNXKDI          1       /* support kdi files            */
 384
 385 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 386
 387 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 388 #define CONFIG_LOOPW            1       /* enable loopw command         */
 389 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 390 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 391 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 392
 393 /*-----------------------------------------------------------------------
 394  * PCI stuff
 395  *-----------------------------------------------------------------------
 396  */
 397 /* General PCI */
 398 #define CONFIG_PCI                      /* include pci support          */
 399 #undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 400 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 401 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 402
 403 /* Board-specific PCI */
 404 #define CFG_PCI_TARGET_INIT
 405 #define CFG_PCI_MASTER_INIT
 406
 407 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 408 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever */
 409
 410 /*
 411  * For booting Linux, the board info and command line data
 412  * have to be in the first 8 MB of memory, since this is
 413  * the maximum mapped by the Linux kernel during initialization.
 414  */
 415 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 416
 417 /*
 418  * Internal Definitions
 419  *
 420  * Boot Flags
 421  */
 422 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 423 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 424
 425 #if defined(CONFIG_CMD_KGDB)
 426 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 427 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 428 #endif
 429 #endif  /* __CONFIG_H */