common/cyclon2.c

   1 /*
   2  * (C) Copyright 2006
   3  * Heiko Schocher, hs@denx.de
   4  * Based on ACE1XK.c
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  *
  24  */
  25
  26 #include <common.h>             /* core U-Boot definitions */
  27 #include <altera.h>
  28 #include <ACEX1K.h>             /* ACEX device family */
  29
  30 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
  31
  32 /* Define FPGA_DEBUG to get debug printf's */
  33 #ifdef  FPGA_DEBUG
  34 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  35 #else
  36 #define PRINTF(fmt,args...)
  37 #endif
  38
  39 /* Note: The assumption is that we cannot possibly run fast enough to
  40  * overrun the device (the Slave Parallel mode can free run at 50MHz).
  41  * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  42  * the board config file to slow things down.
  43  */
  44 #ifndef CONFIG_FPGA_DELAY
  45 #define CONFIG_FPGA_DELAY()
  46 #endif
  47
  48 #ifndef CFG_FPGA_WAIT
  49 #define CFG_FPGA_WAIT CFG_HZ/10         /* 100 ms */
  50 #endif
  51
  52 static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
  53 static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
  54 /* static int CYC2_ps_info( Altera_desc *desc ); */
  55 static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset );
  56
  57 /* ------------------------------------------------------------------------- */
  58 /* CYCLON2 Generic Implementation */
  59 int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
  60 {
  61         int ret_val = FPGA_FAIL;
  62
  63         switch (desc->iface) {
  64         case passive_serial:
  65                 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
  66                 ret_val = CYC2_ps_load (desc, buf, bsize);
  67                 break;
  68
  69                 /* Add new interface types here */
  70
  71         default:
  72                 printf ("%s: Unsupported interface type, %d\n",
  73                                 __FUNCTION__, desc->iface);
  74         }
  75
  76         return ret_val;
  77 }
  78
  79 int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
  80 {
  81         int ret_val = FPGA_FAIL;
  82
  83         switch (desc->iface) {
  84         case passive_serial:
  85                 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
  86                 ret_val = CYC2_ps_dump (desc, buf, bsize);
  87                 break;
  88
  89                 /* Add new interface types here */
  90
  91         default:
  92                 printf ("%s: Unsupported interface type, %d\n",
  93                                 __FUNCTION__, desc->iface);
  94         }
  95
  96         return ret_val;
  97 }
  98
  99 int CYC2_info( Altera_desc *desc )
 100 {
 101         return FPGA_SUCCESS;
 102 }
 103
 104 int CYC2_reloc (Altera_desc * desc, ulong reloc_offset)
 105 {
 106         int ret_val = FPGA_FAIL;        /* assume a failure */
 107
 108         if (desc->family != Altera_CYC2) {
 109                 printf ("%s: Unsupported family type, %d\n",
 110                                 __FUNCTION__, desc->family);
 111                 return FPGA_FAIL;
 112         } else
 113                 switch (desc->iface) {
 114                 case passive_serial:
 115                         ret_val = CYC2_ps_reloc (desc, reloc_offset);
 116                         break;
 117
 118                 /* Add new interface types here */
 119
 120                 default:
 121                         printf ("%s: Unsupported interface type, %d\n",
 122                                         __FUNCTION__, desc->iface);
 123                 }
 124
 125         return ret_val;
 126 }
 127
 128 /* ------------------------------------------------------------------------- */
 129 /* CYCLON2 Passive Serial Generic Implementation                                  */
 130 static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
 131 {
 132         int ret_val = FPGA_FAIL;        /* assume the worst */
 133         Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
 134         int     ret = 0;
 135
 136         PRINTF ("%s: start with interface functions @ 0x%p\n",
 137                         __FUNCTION__, fn);
 138
 139         if (fn) {
 140                 int cookie = desc->cookie;      /* make a local copy */
 141                 unsigned long ts;               /* timestamp */
 142
 143                 PRINTF ("%s: Function Table:\n"
 144                                 "ptr:\t0x%p\n"
 145                                 "struct: 0x%p\n"
 146                                 "config:\t0x%p\n"
 147                                 "status:\t0x%p\n"
 148                                 "write:\t0x%p\n"
 149                                 "done:\t0x%p\n\n",
 150                                 __FUNCTION__, &fn, fn, fn->config, fn->status,
 151                                 fn->write, fn->done);
 152 #ifdef CFG_FPGA_PROG_FEEDBACK
 153                 printf ("Loading FPGA Device %d...", cookie);
 154 #endif
 155
 156                 /*
 157                  * Run the pre configuration function if there is one.
 158                  */
 159                 if (*fn->pre) {
 160                         (*fn->pre) (cookie);
 161                 }
 162
 163                 /* Establish the initial state */
 164                 (*fn->config) (TRUE, TRUE, cookie);     /* Assert nCONFIG */
 165
 166                 udelay(2);              /* T_cfg > 2us  */
 167
 168                 /* Wait for nSTATUS to be asserted */
 169                 ts = get_timer (0);             /* get current time */
 170                 do {
 171                         CONFIG_FPGA_DELAY ();
 172                         if (get_timer (ts) > CFG_FPGA_WAIT) {   /* check the time */
 173                                 puts ("** Timeout waiting for STATUS to go high.\n");
 174                                 (*fn->abort) (cookie);
 175                                 return FPGA_FAIL;
 176                         }
 177                 } while (!(*fn->status) (cookie));
 178
 179                 /* Get ready for the burn */
 180                 CONFIG_FPGA_DELAY ();
 181
 182                 ret = (*fn->write) (buf, bsize, TRUE, cookie);
 183                 if (ret) {
 184                         puts ("** Write failed.\n");
 185                         (*fn->abort) (cookie);
 186                         return FPGA_FAIL;
 187                 }
 188 #ifdef CFG_FPGA_PROG_FEEDBACK
 189                 puts(" OK? ...");
 190 #endif
 191
 192                 CONFIG_FPGA_DELAY ();
 193
 194 #ifdef CFG_FPGA_PROG_FEEDBACK
 195                 putc (' ');                     /* terminate the dotted line */
 196 #endif
 197
 198         /*
 199          * Checking FPGA's CONF_DONE signal - correctly booted ?
 200          */
 201
 202         if ( ! (*fn->done) (cookie) ) {
 203                 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
 204                 (*fn->abort) (cookie);
 205                 return (FPGA_FAIL);
 206         }
 207 #ifdef CFG_FPGA_PROG_FEEDBACK
 208         puts(" OK\n");
 209 #endif
 210
 211         ret_val = FPGA_SUCCESS;
 212
 213 #ifdef CFG_FPGA_PROG_FEEDBACK
 214         if (ret_val == FPGA_SUCCESS) {
 215                 puts ("Done.\n");
 216         }
 217         else {
 218                 puts ("Fail.\n");
 219         }
 220 #endif
 221         (*fn->post) (cookie);
 222
 223         } else {
 224                 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
 225         }
 226
 227         return ret_val;
 228 }
 229
 230 static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
 231 {
 232         /* Readback is only available through the Slave Parallel and         */
 233         /* boundary-scan interfaces.                                         */
 234         printf ("%s: Passive Serial Dumping is unavailable\n",
 235                         __FUNCTION__);
 236         return FPGA_FAIL;
 237 }
 238
 239 static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
 240 {
 241         int ret_val = FPGA_FAIL;        /* assume the worst */
 242         Altera_CYC2_Passive_Serial_fns *fn_r, *fn =
 243                         (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns);
 244
 245         if (fn) {
 246                 ulong addr;
 247
 248                 /* Get the relocated table address */
 249                 addr = (ulong) fn + reloc_offset;
 250                 fn_r = (Altera_CYC2_Passive_Serial_fns *) addr;
 251
 252                 if (!fn_r->relocated) {
 253
 254                         if (memcmp (fn_r, fn,
 255                                                 sizeof (Altera_CYC2_Passive_Serial_fns))
 256                                 == 0) {
 257                                 /* good copy of the table, fix the descriptor pointer */
 258                                 desc->iface_fns = fn_r;
 259                         } else {
 260                                 PRINTF ("%s: Invalid function table at 0x%p\n",
 261                                                 __FUNCTION__, fn_r);
 262                                 return FPGA_FAIL;
 263                         }
 264
 265                         PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
 266                                         desc);
 267
 268                         addr = (ulong) (fn->pre) + reloc_offset;
 269                         fn_r->pre = (Altera_pre_fn) addr;
 270
 271                         addr = (ulong) (fn->config) + reloc_offset;
 272                         fn_r->config = (Altera_config_fn) addr;
 273
 274                         addr = (ulong) (fn->status) + reloc_offset;
 275                         fn_r->status = (Altera_status_fn) addr;
 276
 277                         addr = (ulong) (fn->done) + reloc_offset;
 278                         fn_r->done = (Altera_done_fn) addr;
 279
 280                         addr = (ulong) (fn->write) + reloc_offset;
 281                         fn_r->write = (Altera_write_fn) addr;
 282
 283                         addr = (ulong) (fn->abort) + reloc_offset;
 284                         fn_r->abort = (Altera_abort_fn) addr;
 285
 286                         addr = (ulong) (fn->post) + reloc_offset;
 287                         fn_r->post = (Altera_post_fn) addr;
 288
 289                         fn_r->relocated = TRUE;
 290
 291                 } else {
 292                         /* this table has already been moved */
 293                         /* XXX - should check to see if the descriptor is correct */
 294                         desc->iface_fns = fn_r;
 295                 }
 296
 297                 ret_val = FPGA_SUCCESS;
 298         } else {
 299                 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
 300         }
 301
 302         return ret_val;
 303 }
 304
 305 #endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */