2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
6 * board/cradle/lowlevel_init.S for another PXA250 setup that is
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/pxa-regs.h>
32 DRAM_SIZE: .long CFG_DRAM_SIZE
34 /* wait for coprocessor write complete */
36 mrc p15,0,\reg,c2,c0,0
58 /* Set up GPIO pins first ----------------------------------------- */
61 /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
62 ldr r0, =0x40E10438 @ GPIO41 FFRXD
66 ldr r0, =0x40E1043C @ GPIO42 FFTXD
70 ldr r0, =0x40E10440 @ GPIO43 FFCTS
74 ldr r0, =0x40E10444 @ GPIO 44 FFDCD
78 ldr r0, =0x40E10448 @ GPIO 45 FFDSR
82 ldr r0, =0x40E1044C @ GPIO 46 FFRI
86 ldr r0, =0x40E10450 @ GPIO 47 FFDTR
90 ldr r0, =0x40E10454 @ GPIO 48
94 /* tebrandt - ASCR, clear the RDH bit */
97 bic r1, r1, #0x80000000
100 /* ---------------------------------------------------------------- */
101 /* Enable memory interface */
103 /* The sequence below is based on the recommended init steps */
104 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
106 /* ---------------------------------------------------------------- */
108 /* ---------------------------------------------------------------- */
109 /* Step 1: Wait for at least 200 microsedonds to allow internal */
110 /* clocks to settle. Only necessary after hard reset... */
111 /* FIXME: can be optimized later */
112 /* ---------------------------------------------------------------- */
114 /* mk: replaced with wait macro */
115 /* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
118 /* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
119 /* /\* so 0x300 should be plenty *\/ */
128 /* configure the MEMCLKCFG register */
132 ldr r2, [r1] @ DELAY UNTIL WRITTEN
134 /* set CSADRCFG[0] to data flash SRAM mode */
138 ldr r2, [r1] @ DELAY UNTIL WRITTEN
140 /* set CSADRCFG[1] to data flash SRAM mode */
144 ldr r2, [r1] @ DELAY UNTIL WRITTEN
146 /* set MSC 0 register for SRAM memory */
150 ldr r2, [r1] @ DELAY UNTIL WRITTEN
152 /* set CSADRCFG[2] to data flash SRAM mode */
156 ldr r2, [r1] @ DELAY UNTIL WRITTEN
158 /* set CSADRCFG[3] to VLIO mode */
162 ldr r2, [r1] @ DELAY UNTIL WRITTEN
164 /* set MSC 1 register for VLIO memory */
168 ldr r2, [r1] @ DELAY UNTIL WRITTEN
171 /* This does not work in Zylonite. -SC */
178 /* Configure ACCR Register */
184 /* Configure MDCNFG Register */
185 ldr r0, =MDCNFG @ MDCNFG
190 /* Perform Resistive Compensation by configuring RCOMP register */
191 ldr r1, =RCOMP @ RCOMP
196 /* Configure MDMRS Register for SDCS0 */
197 ldr r1, =MDMRS @ MDMRS
204 /* Configure MDMRS Register for SDCS1 */
205 ldr r1, =MDMRS @ MDMRS
212 /* Configure MDREFR */
213 ldr r1, =MDREFR @ MDREFR
224 /* Hardware DDR Read-Strobe Delay Calibration */
225 ldr r0, =DDR_HCAL @ DDR_HCAL
226 ldr r1, =0x803ffc07 @ the offset is correct? -SC
231 /* Here we assume the hardware calibration alwasy be successful. -SC */
232 /* Set DMCEN bit in MDCNFG Register */
233 ldr r0, =MDCNFG @ MDCNFG
235 orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
238 #ifndef CFG_SKIP_DRAM_SCRUB
239 /* scrub/init SDRAM if enabled/present */
240 /* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
241 /* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
242 /* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
243 ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
244 ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
245 mov r0, #0 /* scrub with 0x0000:0000 */
253 10: /* fastScrubLoop */
254 subs r9, r9, #32 /* 32 bytes/line */
258 #endif /* CFG_SKIP_DRAM_SCRUB */
261 /* Mask all interrupts */
263 mcr p6, 0, r1, c1, c0, 0 @ ICMR
265 /* Disable software and data breakpoints */
267 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
268 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
269 mcr p15,0,r0,c14,c4,0 /* dbcon */
271 /* Enable all debug functionality */
273 mcr p14,0,r0,c10,c0,0 /* dcsr */
275 /* We are finished with Intel's memory controller initialisation */
277 /* ---------------------------------------------------------------- */
278 /* End lowlevel_init */
279 /* ---------------------------------------------------------------- */
286 @********************************************************************************
289 @ This function is used to calibrate DQS delay lines.
290 @ Monahans supports three ways to do it. One is software
291 @ calibration. Two is hardware calibration. Three is hybrid
298 @ Case 1: Write the correct delay value once
299 @ Configure DDR_SCAL Register
300 ldr r0, =DDR_SCAL @ DDR_SCAL
301 q ldr r1, =0xaf2f2f2f
305 /* @ Case 2: Software Calibration
306 @ Write test pattern to memory
307 ldr r5, =0x0faf0faf @ Data Pattern
308 ldr r4, =0xa0000000 @ DDR ram
311 mov r1, =0x0 @ delay count
325 orr r3, r3, =0x80000000
344 orr r3, r3, =0x80000000
361 orr r3, r3, =0x80000000
366 @ Case 3: Hardware Calibratoin
367 ldr r0, =DDR_HCAL @ DDR_HCAL
368 ldr r1, =0x803ffc07 @ the offset is correct? -SC