3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/processor.h>
36 typedef struct sdram_conf_s sdram_conf_t
;
38 sdram_conf_t ddr_cs_conf
[] = {
39 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
40 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
41 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
42 {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
45 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
47 int cas_latency(void);
50 * Autodetect onboard DDR SDRAM on 85xx platforms
52 * NOTE: Some of the hardcoded values are hardware dependant,
53 * so this should be extended for other future boards
56 long int sdram_setup(int casl
)
59 volatile ccsr_ddr_t
*ddr
= (void *)(CFG_MPC85xx_DDR_ADDR
);
60 unsigned long cfg_ddr_timing1
;
61 unsigned long cfg_ddr_mode
;
64 * Disable memory controller.
71 cfg_ddr_timing1
= 0x47405331 | (3 << 16);
72 cfg_ddr_mode
= 0x40020002 | (2 << 4);
76 cfg_ddr_timing1
= 0x47405331 | (4 << 16);
77 cfg_ddr_mode
= 0x40020002 | (6 << 4);
82 cfg_ddr_timing1
= 0x47405331 | (5 << 16);
83 cfg_ddr_mode
= 0x40020002 | (3 << 4);
87 ddr
->cs0_bnds
= (ddr_cs_conf
[0].size
- 1) >> 24;
88 ddr
->cs0_config
= ddr_cs_conf
[0].reg
;
89 ddr
->timing_cfg_1
= cfg_ddr_timing1
;
90 ddr
->timing_cfg_2
= 0x00000800; /* P9-45,may need tuning */
91 ddr
->sdram_mode
= cfg_ddr_mode
;
92 ddr
->sdram_interval
= 0x05160100; /* autocharge,no open page */
93 ddr
->err_disable
= 0x0000000D;
95 asm ("sync;isync;msync");
98 ddr
->sdram_cfg
= 0xc2000000; /* unbuffered,no DYN_PWR */
99 asm ("sync; isync; msync");
102 for (i
=0; i
<N_DDR_CS_CONF
; i
++) {
103 ddr
->cs0_config
= ddr_cs_conf
[i
].reg
;
105 if (get_ram_size(0, ddr_cs_conf
[i
].size
) == ddr_cs_conf
[i
].size
) {
107 * OK, size detected -> all done
109 return ddr_cs_conf
[i
].size
;
113 return 0; /* nothing found ! */
116 void board_add_ram_info(int use_default
)
121 casl
= CONFIG_DDR_DEFAULT_CL
;
123 casl
= cas_latency();
141 long int initdram (int board_type
)
146 #if defined(CONFIG_DDR_DLL)
148 * This DLL-Override only used on TQM8540 and TQM8560
151 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
157 * Work around to stabilize DDR DLL
159 gur
->ddrdllcr
= 0x81000000;
160 asm("sync;isync;msync");
162 while (gur
->ddrdllcr
!= 0x81000100) {
163 gur
->devdisr
= gur
->devdisr
| 0x00010000;
164 asm("sync;isync;msync");
167 gur
->devdisr
= gur
->devdisr
& 0xfff7ffff;
168 asm("sync;isync;msync");
174 casl
= cas_latency();
175 dram_size
= sdram_setup(casl
);
176 if ((dram_size
== 0) && (casl
!= CONFIG_DDR_DEFAULT_CL
)) {
178 * Try again with default CAS latency
180 puts("Problem with CAS lantency");
181 board_add_ram_info(1);
182 puts(", using default CL!\n");
183 casl
= CONFIG_DDR_DEFAULT_CL
;
184 dram_size
= sdram_setup(casl
);
191 #if defined(CFG_DRAM_TEST)
194 uint
*pstart
= (uint
*) CFG_MEMTEST_START
;
195 uint
*pend
= (uint
*) CFG_MEMTEST_END
;
198 printf ("SDRAM test phase 1:\n");
199 for (p
= pstart
; p
< pend
; p
++)
202 for (p
= pstart
; p
< pend
; p
++) {
203 if (*p
!= 0xaaaaaaaa) {
204 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
209 printf ("SDRAM test phase 2:\n");
210 for (p
= pstart
; p
< pend
; p
++)
213 for (p
= pstart
; p
< pend
; p
++) {
214 if (*p
!= 0x55555555) {
215 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
220 printf ("SDRAM test passed.\n");