board/snmc/qs850/qs850.c

   1 /*
   2  * (C) Copyright 2003
   3  * MuLogic B.V.
   4  *
   5  * (C) Copyright 2002
   6  * Simple Network Magic Corporation, dnevil@snmc.com
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <asm/u-boot.h>
  32 #include <commproc.h>
  33 #include "mpc8xx.h"
  34
  35 /* ------------------------------------------------------------------------- */
  36
  37 static long  int dram_size (long int, long int *, long int);
  38
  39 /* ------------------------------------------------------------------------- */
  40
  41 const uint sdram_table[] =
  42 {
  43         /*
  44          * Single Read. (Offset 0 in UPMA RAM)
  45          */
  46         0x0f07cc04,  0x00adcc04,  0x00a74c00,  0x00bfcc04,
  47         0x1fffcc05,  0xffffcc05,  0xffffcc05,  0xffffcc05,
  48         /*
  49          * Burst Read. (Offset 8 in UPMA RAM)
  50          */
  51         0x0ff7fc04,  0x0ffffc04,  0x00bdfc04,  0x00fffc00,
  52         0x00fffc00,  0x00fffc00,  0x0ff77c00,  0x1ffffc05,
  53         0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
  54         0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
  55         /*
  56          * Single Write. (Offset 18 in UPMA RAM)
  57          */
  58         0x0f07cc04,  0x0fafcc00,  0x01ad0c04,  0x1ff74c07,
  59         0xffffcc05,  0xffffcc05,  0xffffcc05,  0xffffcc05,
  60         /*
  61          * Burst Write. (Offset 20 in UPMA RAM)
  62          */
  63         0x0ff7fc04,  0x0ffffc00,  0x00bd7c00,  0x00fffc00,
  64         0x00fffc00,  0x00fffc00,  0x0ffffc04,  0x0ff77c04,
  65         0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
  66         0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
  67         /*
  68          * Refresh  (Offset 30 in UPMA RAM)
  69          */
  70         0xffffcc04,  0x1ff5cc84,  0xffffcc04,  0xffffcc04,
  71         0xffffcc84,  0xffffcc05,  0xffffcc04,  0xffffcc04,
  72         0xffffcc04,  0xffffcc04,  0xffffcc04,  0xffffcc04,
  73         /*
  74          * Exception. (Offset 3c in UPMA RAM)
  75          */
  76         0x1ff74c04,  0xffffcc07,  0xffffaa34,  0x1fb54a37
  77 };
  78
  79 /* ------------------------------------------------------------------------- */
  80
  81
  82 /*
  83  * Check Board Identity:
  84  *
  85  * Test ID string (QS850, QS823, ...)
  86  *
  87  * Always return 1
  88  */
  89
  90 int checkboard (void)
  91 {
  92         char *s, *e;
  93         char buf[64];
  94         int i;
  95
  96         i = getenv_r("serial#", buf, sizeof(buf));
  97         s = (i>0) ? buf : NULL;
  98
  99 #ifdef CONFIG_QS850
 100         if (!s || strncmp(s, "QS850", 5)) {
 101                 puts ("### No HW ID - assuming QS850");
 102 #endif
 103 #ifdef CONFIG_QS823
 104         if (!s || strncmp(s, "QS823", 5)) {
 105                 puts ("### No HW ID - assuming QS823");
 106 #endif
 107         } else {
 108                 for (e=s; *e; ++e) {
 109                 if (*e == ' ')
 110                 break;
 111         }
 112
 113         for ( ; s<e; ++s) {
 114                 putc (*s);
 115                 }
 116         }
 117         putc ('\n');
 118
 119         return (0);
 120 }
 121
 122 /* ------------------------------------------------------------------------- */
 123 /* SDRAM Mode Register Definitions */
 124
 125 /* Set SDRAM Burst Length to 4 (010) */
 126 /* See Motorola MPC850 User Manual, Page 13-14 */
 127 #define SDRAM_BURST_LENGTH      (2)
 128
 129 /* Set Wrap Type to Sequential (0) */
 130 /* See Motorola MPC850 User Manual, Page 13-14 */
 131 #define SDRAM_WRAP_TYPE         (0 << 3)
 132
 133 /* Set /CAS Latentcy to 2 clocks */
 134 #define SDRAM_CAS_LATENTCY      (2 << 4)
 135
 136 /* The Mode Register value must be shifted left by 2, since it is */
 137 /* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
 138 #define SDRAM_MODE_REG  ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
 139
 140 #define UPMA_RUN(loops,index)   (0x80002000 + (loops<<8) + index)
 141
 142 /* Please note a value of zero = 16 loops */
 143 #define REFRESH_INIT_LOOPS (0)
 144
 145
 146 long int initdram (int board_type)
 147 {
 148         volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
 149         volatile memctl8xx_t *memctl = &immap->im_memctl;
 150         long int size;
 151
 152         upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 153
 154         /*
 155         * Prescaler for refresh
 156         */
 157         memctl->memc_mptpr = CFG_MPTPR;
 158
 159         /*
 160         * Map controller bank 1 to the SDRAM address
 161         */
 162         memctl->memc_or1 = CFG_OR1;
 163         memctl->memc_br1 = CFG_BR1;
 164         udelay(1000);
 165
 166         /* perform SDRAM initialization sequence */
 167         memctl->memc_mamr = CFG_16M_MAMR;
 168         udelay(100);
 169
 170         /* Program the SDRAM's Mode Register */
 171         memctl->memc_mar  = SDRAM_MODE_REG;
 172
 173         /* Run the Prechard Pattern at 0x3C */
 174         memctl->memc_mcr  = UPMA_RUN(1,0x3c);
 175         udelay(1);
 176
 177         /* Run the Refresh program residing at MAD index 0x30 */
 178         /* This contains the CBR Refresh command with a loop */
 179         /* The SDRAM must be refreshed at least 2 times */
 180         /* Please note a value of zero = 16 loops */
 181         memctl->memc_mcr  = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
 182         udelay(1);
 183
 184         /* Run the Exception program residing at MAD index 0x3E */
 185         /* This contains the Write Mode Register command */
 186         /* The Write Mode Register command uses the value written to MAR */
 187         memctl->memc_mcr  = UPMA_RUN(1,0x3e);
 188
 189         udelay (1000);
 190
 191         /*
 192         * Check for 32M SDRAM Memory Size
 193         */
 194         size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
 195         (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
 196         udelay (1000);
 197
 198         /*
 199         * Check for 16M SDRAM Memory Size
 200         */
 201         if (size != SDRAM_32M_MAX_SIZE) {
 202         size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
 203         (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
 204         udelay (1000);
 205         }
 206
 207         udelay(10000);
 208         return (size);
 209 }
 210
 211 /* ------------------------------------------------------------------------- */
 212
 213 /*
 214  * Check memory range for valid RAM. A simple memory test determines
 215  * the actually available RAM size between addresses `base' and
 216  * `base + maxsize'. Some (not all) hardware errors are detected:
 217  * - short between address lines
 218  * - short between data lines
 219  */
 220
 221 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 222 {
 223         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 224         volatile memctl8xx_t *memctl = &immap->im_memctl;
 225
 226         memctl->memc_mamr = mamr_value;
 227
 228         return (get_ram_size(base, maxsize));
 229 }