6 * Simple Network Magic Corporation, dnevil@snmc.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/u-boot.h>
35 /* ------------------------------------------------------------------------- */
37 static long int dram_size (long int, long int *, long int);
39 /* ------------------------------------------------------------------------- */
41 const uint sdram_table
[] =
44 * Single Read. (Offset 0 in UPMA RAM)
46 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04,
47 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
49 * Burst Read. (Offset 8 in UPMA RAM)
51 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
52 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
53 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
54 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
56 * Single Write. (Offset 18 in UPMA RAM)
58 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07,
59 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
61 * Burst Write. (Offset 20 in UPMA RAM)
63 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
64 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04,
65 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
66 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
68 * Refresh (Offset 30 in UPMA RAM)
70 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04,
71 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04,
72 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04,
74 * Exception. (Offset 3c in UPMA RAM)
76 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37
79 /* ------------------------------------------------------------------------- */
83 * Check Board Identity:
85 * Test ID string (QS850, QS823, ...)
96 i
= getenv_r("serial#", buf
, sizeof(buf
));
97 s
= (i
>0) ? buf
: NULL
;
100 if (!s
|| strncmp(s
, "QS850", 5)) {
101 puts ("### No HW ID - assuming QS850");
104 if (!s
|| strncmp(s
, "QS823", 5)) {
105 puts ("### No HW ID - assuming QS823");
122 /* ------------------------------------------------------------------------- */
123 /* SDRAM Mode Register Definitions */
125 /* Set SDRAM Burst Length to 4 (010) */
126 /* See Motorola MPC850 User Manual, Page 13-14 */
127 #define SDRAM_BURST_LENGTH (2)
129 /* Set Wrap Type to Sequential (0) */
130 /* See Motorola MPC850 User Manual, Page 13-14 */
131 #define SDRAM_WRAP_TYPE (0 << 3)
133 /* Set /CAS Latentcy to 2 clocks */
134 #define SDRAM_CAS_LATENTCY (2 << 4)
136 /* The Mode Register value must be shifted left by 2, since it is */
137 /* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
138 #define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
140 #define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index)
142 /* Please note a value of zero = 16 loops */
143 #define REFRESH_INIT_LOOPS (0)
146 long int initdram (int board_type
)
148 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
149 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
152 upmconfig(UPMA
, (uint
*)sdram_table
, sizeof(sdram_table
)/sizeof(uint
));
155 * Prescaler for refresh
157 memctl
->memc_mptpr
= CFG_MPTPR
;
160 * Map controller bank 1 to the SDRAM address
162 memctl
->memc_or1
= CFG_OR1
;
163 memctl
->memc_br1
= CFG_BR1
;
166 /* perform SDRAM initialization sequence */
167 memctl
->memc_mamr
= CFG_16M_MAMR
;
170 /* Program the SDRAM's Mode Register */
171 memctl
->memc_mar
= SDRAM_MODE_REG
;
173 /* Run the Prechard Pattern at 0x3C */
174 memctl
->memc_mcr
= UPMA_RUN(1,0x3c);
177 /* Run the Refresh program residing at MAD index 0x30 */
178 /* This contains the CBR Refresh command with a loop */
179 /* The SDRAM must be refreshed at least 2 times */
180 /* Please note a value of zero = 16 loops */
181 memctl
->memc_mcr
= UPMA_RUN(REFRESH_INIT_LOOPS
,0x30);
184 /* Run the Exception program residing at MAD index 0x3E */
185 /* This contains the Write Mode Register command */
186 /* The Write Mode Register command uses the value written to MAR */
187 memctl
->memc_mcr
= UPMA_RUN(1,0x3e);
192 * Check for 32M SDRAM Memory Size
194 size
= dram_size(CFG_32M_MAMR
|MAMR_PTAE
,
195 (long *)SDRAM_BASE
, SDRAM_32M_MAX_SIZE
);
199 * Check for 16M SDRAM Memory Size
201 if (size
!= SDRAM_32M_MAX_SIZE
) {
202 size
= dram_size(CFG_16M_MAMR
|MAMR_PTAE
,
203 (long *)SDRAM_BASE
, SDRAM_16M_MAX_SIZE
);
211 /* ------------------------------------------------------------------------- */
214 * Check memory range for valid RAM. A simple memory test determines
215 * the actually available RAM size between addresses `base' and
216 * `base + maxsize'. Some (not all) hardware errors are detected:
217 * - short between address lines
218 * - short between data lines
221 static long int dram_size (long int mamr_value
, long int *base
, long int maxsize
)
223 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
224 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
226 memctl
->memc_mamr
= mamr_value
;
228 return (get_ram_size(base
, maxsize
));