2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 #include <asm/arch/mx31-regs.h>
42 /* RedBoot: AIPS setup - Only setup MPROTx registers.
43 * The PACR default values are good.*/
46 * Set all MPROTx to be non-bufferable, trusted for R/W,
47 * not forced to user-mode.
58 * Clear the on and off peripheral modules Supervisor Protect bit
59 * for SDMA to access them. Did not change the AIPS control registers
60 * (offset 0x20) access type
69 and r1, r1, #0x00FFFFFF
79 and r1, r1, #0x00FFFFFF
83 /* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
86 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
88 str r1, [r0, #0x000] /* for S0 */
89 str r1, [r0, #0x100] /* for S1 */
90 str r1, [r0, #0x200] /* for S2 */
91 str r1, [r0, #0x300] /* for S3 */
92 str r1, [r0, #0x400] /* for S4 */
93 /* SGPCR - always park on last master */
95 str r1, [r0, #0x010] /* for S0 */
96 str r1, [r0, #0x110] /* for S1 */
97 str r1, [r0, #0x210] /* for S2 */
98 str r1, [r0, #0x310] /* for S3 */
99 str r1, [r0, #0x410] /* for S4 */
100 /* MGPCR - restore default values */
102 str r1, [r0, #0x800] /* for M0 */
103 str r1, [r0, #0x900] /* for M1 */
104 str r1, [r0, #0xA00] /* for M2 */
105 str r1, [r0, #0xB00] /* for M3 */
106 str r1, [r0, #0xC00] /* for M4 */
107 str r1, [r0, #0xD00] /* for M5 */
110 /* RedBoot: M3IF setup */
112 /* Configure M3IF registers */
115 * M3IF Control Register (M3IFCTL)
116 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
117 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
118 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
119 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
120 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
121 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
122 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
123 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
128 str r0, [r1] /* M3IF control reg */
129 .endm /* init_m3if */
131 /* RedBoot: To support 133MHz DDR */
132 .macro init_drive_strength
134 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
135 * in SW_PAD_CTL registers
141 bic r0, r0, #(1 << 12)
146 bic r0, r0, #(1 << 22)
151 bic r0, r0, #(1 << 2)
156 bic r0, r0, #(1 << 22)
161 bic r0, r0, #(1 << 22)
164 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
165 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
168 bic r0, r0, #(1 << 22)
169 bic r0, r0, #(1 << 12)
170 bic r0, r0, #(1 << 2)
175 .endm /* init_drive_strength */
177 /* CPLD on CS4 setup */
191 /* Redboot initializes very early AIPS, what for?
192 * Then it also initializes Multi-Layer AHB Crossbar Switch,
194 /* Also setup the Peripheral Port Remap register inside the core */
195 ldr r0, =0x40000015 /* start from AIPS 2GB region */
196 mcr p15, 0, r0, c15, c2, 4
208 /* Image Processing Unit: */
209 /* Too early to switch display on? */
210 /* Switch on Display Interface */
211 REG IPU_CONF, IPU_CONF_DI_EN
212 /* Clock Control Module: */
213 /* Use CKIH, MCU PLL off */
214 REG CCM_CCMR, 0x074B0BF5
218 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
219 /* Switch to MCU PLL */
220 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
222 /* PBC CPLD on CS4 */
225 /* Is 27MHz switch set? */
233 ldreq r1, MPCTL_PARAM_532
234 ldrne r1, MPCTL_PARAM_532_27
238 /* Set UPLL=240MHz, USB=60MHz */
242 ldreq r1, UPCTL_PARAM_240
243 ldrne r1, UPCTL_PARAM_240_27
246 /* default CLKO to 1/8 of the ARM core */
248 add r1, r1, #0x00000006
252 /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
253 /* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
254 PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | \
255 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | \
258 /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
259 /* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | \
261 /* Default: 1, 4, 12, 1 */
262 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
264 /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
265 REG 0xB8001010, 0x00000004
266 REG 0xB8001004, 0x006ac73a
267 REG 0xB8001000, 0x92100000
268 REG 0x80000f00, 0x12344321
269 REG 0xB8001000, 0xa2100000
270 REG 0x80000000, 0x12344321
271 REG 0x80000000, 0x12344321
272 REG 0xB8001000, 0xb2100000
273 REG8 0x80000033, 0xda
274 REG8 0x81000000, 0xff
275 REG 0xB8001000, 0x82226080
276 REG 0x80000000, 0xDEADBEEF
277 REG 0xB8001010, 0x0000000c
282 .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
284 .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
286 .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
288 .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))