3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
35 DECLARE_GLOBAL_DATA_PTR
;
37 const uint sdram_table
[] =
39 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
40 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
42 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
43 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
44 /* 0x10 Load mode register */
45 0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
46 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
47 /* 0x18 Single Write */
48 0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
49 0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
50 /* 0x20 Burst Write */
51 0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
52 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
53 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
54 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
55 /* 0x30 Precharge all and Refresh */
56 0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
57 0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
58 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
60 0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
65 puts ("Board: Keymile mgsuvd\n");
69 long int initdram (int board_type
)
71 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
72 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
75 upmconfig (UPMB
, (uint
*) sdram_table
,
76 sizeof (sdram_table
) / sizeof (uint
));
79 * Preliminary prescaler for refresh (depends on number of
80 * banks): This value is selected for four cycles every 62.4 us
81 * with two SDRAM banks or four cycles every 31.2 us with one
82 * bank. It will be adjusted after memory sizing.
84 memctl
->memc_mptpr
= CFG_MPTPR
;
87 * The following value is used as an address (i.e. opcode) for
88 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
89 * the port size is 32bit the SDRAM does NOT "see" the lower two
90 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
93 * | | | | +- Burst Length = 4
94 * | | | +----- Burst Type = Sequential
95 * | | +------- CAS Latency = 2
96 * | +----------- Operating Mode = Standard
97 * +-------------- Write Burst Mode = Programmed Burst Length
99 memctl
->memc_mar
= CFG_MAR
;
102 * Map controller banks 1 to the SDRAM banks 1 at
103 * preliminary addresses - these have to be modified after the
104 * SDRAM size has been determined.
106 memctl
->memc_or1
= CFG_OR1_PRELIM
;
107 memctl
->memc_br1
= CFG_BR1_PRELIM
;
109 memctl
->memc_mbmr
= CFG_MBMR
& (~(MBMR_PTBE
)); /* no refresh yet */
113 /* perform SDRAM initializsation sequence */
115 memctl
->memc_mcr
= 0x80802830; /* SDRAM bank 0 */
117 memctl
->memc_mcr
= 0x80802110; /* SDRAM bank 0 - execute twice */
120 memctl
->memc_mbmr
|= MBMR_PTBE
; /* enable refresh */
125 * Check Bank 0 Memory Size for re-configuration
128 size
= get_ram_size(SDRAM_BASE1_PRELIM
, SDRAM_MAX_SIZE
);
132 debug ("SDRAM Bank 0: %ld MB\n", size
>> 20);
138 * Early board initalization.
140 int board_early_init_r(void)
142 /* setup the UPIOx */
143 *(char *)(CFG_PIGGY_BASE
+ 0x02) = 0xc0;
144 *(char *)(CFG_PIGGY_BASE
+ 0x03) = 0x35;
148 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
150 * update "memory" property in the blob
152 void ft_blob_update(void *blob
, bd_t
*bd
)
154 int ret
, nodeoffset
= 0;
155 ulong brg_data
[1] = {0};
156 ulong memory_data
[2] = {0};
157 ulong flash_data
[4] = {0};
159 memory_data
[0] = cpu_to_be32(bd
->bi_memstart
);
160 memory_data
[1] = cpu_to_be32(bd
->bi_memsize
);
162 nodeoffset
= fdt_path_offset (blob
, "/memory");
163 if (nodeoffset
>= 0) {
164 ret
= fdt_setprop(blob
, nodeoffset
, "reg", memory_data
,
165 sizeof(memory_data
));
167 printf("ft_blob_update): cannot set /memory/reg "
168 "property err:%s\n", fdt_strerror(ret
));
171 /* memory node is required in dts */
172 printf("ft_blob_update(): cannot find /memory node "
173 "err:%s\n", fdt_strerror(nodeoffset
));
176 flash_data
[2] = cpu_to_be32(bd
->bi_flashstart
);
177 flash_data
[3] = cpu_to_be32(bd
->bi_flashsize
);
178 nodeoffset
= fdt_path_offset (blob
, "/localbus");
179 if (nodeoffset
>= 0) {
180 ret
= fdt_setprop(blob
, nodeoffset
, "ranges", flash_data
,
183 printf("ft_blob_update): cannot set /localbus/ranges "
184 "property err:%s\n", fdt_strerror(ret
));
187 /* memory node is required in dts */
188 printf("ft_blob_update(): cannot find /localbus node "
189 "err:%s\n", fdt_strerror(nodeoffset
));
192 brg_data
[0] = cpu_to_be32(bd
->bi_busfreq
);
193 nodeoffset
= fdt_path_offset (blob
, "/soc/cpm");
194 if (nodeoffset
>= 0) {
195 ret
= fdt_setprop(blob
, nodeoffset
, "brg-frequency", brg_data
,
198 printf("ft_blob_update): cannot set /soc/cpm/brg-frequency "
199 "property err:%s\n", fdt_strerror(ret
));
202 /* memory node is required in dts */
203 printf("ft_blob_update(): cannot find /soc/cpm node "
204 "err:%s\n", fdt_strerror(nodeoffset
));
207 nodeoffset
= fdt_path_offset (blob
, "/soc/cpm/ethernet");
208 if (nodeoffset
>= 0) {
209 ret
= fdt_setprop(blob
, nodeoffset
, "mac-address", bd
->bi_enetaddr
,
212 printf("ft_blob_update): cannot set /soc/cpm/scc/mac-address "
213 "property err:%s\n", fdt_strerror(ret
));
216 /* memory node is required in dts */
217 printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
218 "err:%s\n", fdt_strerror(nodeoffset
));
222 void ft_board_setup(void *blob
, bd_t
*bd
)
224 ft_cpu_setup( blob
, bd
);
225 ft_blob_update(blob
, bd
);
227 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */