board/hxd8/hxd8.c

   1 /*
   2  * (C) Copyright 2007 by OpenMoko, Inc.
   3  * Author: Harald Welte <laforge@openmoko.org>
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2002
  10  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <video_fb.h>
  33 #include <nand.h>
  34 #include <pcf50606.h>
  35 #include <s3c2440.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #define FCLK_SPEED 1
  40
  41 #if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
  42 #define M_MDIV  0xC3
  43 #define M_PDIV  0x4
  44 #define M_SDIV  0x1
  45 #elif FCLK_SPEED==1
  46 #if 0
  47 #define M_MDIV  0x6e    /* Fout = 399.65MHz */
  48 #define M_PDIV  0x3
  49 #define M_SDIV  0x1
  50 #else
  51 #define M_MDIV  0x61    /* Fout = 296.35MHz due to wrong PLL capacitors */
  52 #define M_PDIV  0x1
  53 #define M_SDIV  0x2
  54 #endif
  55 #endif
  56
  57 #define USB_CLOCK 1
  58
  59 #if USB_CLOCK==0
  60 #define U_M_MDIV        0xA1
  61 #define U_M_PDIV        0x3
  62 #define U_M_SDIV        0x1
  63 #elif USB_CLOCK==1
  64 #define U_M_MDIV        0x3c
  65 #define U_M_PDIV        0x4
  66 #define U_M_SDIV        0x2
  67 #endif
  68
  69 static inline void delay (unsigned long loops)
  70 {
  71         __asm__ volatile ("1:\n"
  72           "subs %0, %1, #1\n"
  73           "bne 1b":"=r" (loops):"0" (loops));
  74 }
  75
  76 /*
  77  * Miscellaneous platform dependent initialisations
  78  */
  79
  80 int board_init (void)
  81 {
  82         S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  83         S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  84
  85         /* to reduce PLL lock time, adjust the LOCKTIME register */
  86         clk_power->LOCKTIME = 0xFFFFFF;
  87
  88         /* configure MPLL */
  89         clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
  90
  91         /* some delay between MPLL and UPLL */
  92         delay (4000);
  93
  94         /* configure UPLL */
  95         clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
  96
  97         /* some delay between MPLL and UPLL */
  98         delay (8000);
  99
 100         /* set up the I/O ports */
 101         gpio->GPACON = 0x005E0FFE;
 102         gpio->GPADAT = 0x0001C000;
 103         gpio->GPBCON = 0x00045542;
 104         gpio->GPBUP = 0x000007FF;
 105         gpio->GPCCON = 0xAAAA02A9;
 106         gpio->GPCUP = 0x0000FFFF;
 107         gpio->GPDCON = 0xAAAAAAAA;
 108         gpio->GPDUP = 0x0000FFFF;
 109         gpio->GPECON = 0xAAAAAAAA;
 110         gpio->GPEUP = 0x0000FFFF;
 111         gpio->GPFCON = 0x0000AAA9;
 112         gpio->GPFUP = 0x000000FF;
 113         gpio->GPGCON = 0x027D0316;
 114         gpio->GPGUP = 0x0000FFFF;
 115         gpio->GPHCON = 0x0014AAAA;
 116         gpio->GPHUP = 0x000007FF;
 117         gpio->GPJCON = 0x00000000;
 118
 119         /* USB CHG enable */
 120         gpio->GPGDAT |= ( 1 << 11);
 121 #if 0
 122         /* USB Device Part */
 123         /*GPGCON is reset for USB Device */
 124         gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
 125         gpio->GPGUP = gpio->GPGUP | ( 1 << 12);                 /* Pull up disable */
 126
 127         gpio->GPGDAT |= ( 1 << 12);
 128         gpio->GPGDAT &= ~( 1 << 12);
 129         udelay(20000);
 130         gpio->GPGDAT |= ( 1 << 12);
 131 #endif
 132
 133         /* arch number of SMDK2440-Board */
 134         gd->bd->bi_arch_number = MACH_TYPE_HXD8;
 135
 136         /* adress of boot parameters */
 137         gd->bd->bi_boot_params = 0x30000100;
 138
 139         icache_enable();
 140         dcache_enable();
 141
 142         return 0;
 143 }
 144
 145 void board_video_init(GraphicDevice *pGD)
 146 {
 147         S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
 148
 149         lcd->LCDCON1 = 0x0000057b;
 150         lcd->LCDCON2 = 0x0143c049;
 151         lcd->LCDCON3 = 0x0009df01;
 152         lcd->LCDCON4 = 0x00000028;
 153         lcd->LCDCON5 = 0x00000b08;
 154
 155         lcd->TPAL = 0x01202020;
 156
 157         //lcd->LCDCON5 |= (0x01 << 3);
 158 }
 159
 160 int board_late_init(void)
 161 {
 162         /* Initialize the Power Management Unit with a safe register set */
 163         pcf50606_init();
 164
 165         return 0;
 166 }
 167
 168 int dram_init(void)
 169 {
 170         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 171         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 172
 173         return 0;
 174 }
 175
 176 u_int32_t get_board_rev(void)
 177 {
 178         return 0x00000110;
 179 }
 180
 181 /* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
 182    "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
 183    images: 640*480*2*2 = 1228800 < 1245184. */
 184
 185 unsigned int dynpart_size[] = {
 186     CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3fd00000, 0 };
 187 char *dynpart_names[] = {
 188     "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
 189