board/amcc/sequoia/sequoia.c

   1 /*
   2  * (C) Copyright 2006-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <libfdt.h>
  27 #include <fdt_support.h>
  28 #include <ppc440.h>
  29 #include <asm/gpio.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <asm/bitops.h>
  33 #include <asm/ppc4xx-intvec.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  38
  39 ulong flash_get_size (ulong base, int banknum);
  40
  41 int board_early_init_f(void)
  42 {
  43         u32 sdr0_cust0;
  44         u32 sdr0_pfc1, sdr0_pfc2;
  45         u32 reg;
  46
  47         mtdcr(ebccfga, xbcfg);
  48         mtdcr(ebccfgd, 0xb8400000);
  49
  50         /*
  51          * Setup the interrupt controller polarities, triggers, etc.
  52          */
  53         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  54         mtdcr(uic0er, 0x00000000);      /* disable all */
  55         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
  56         mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
  57         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
  58         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
  59         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  60
  61         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  62         mtdcr(uic1er, 0x00000000);      /* disable all */
  63         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  64         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
  65         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
  66         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
  67         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  68
  69         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  70         mtdcr(uic2er, 0x00000000);      /* disable all */
  71         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
  72         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
  73         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
  74         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
  75         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  76
  77         /* 50MHz tmrclk */
  78         out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
  79
  80         /* clear write protects */
  81         out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
  82
  83         /* enable Ethernet */
  84         out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
  85
  86         /* enable USB device */
  87         out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
  88
  89         /* select Ethernet (and optionally IIC1) pins */
  90         mfsdr(SDR0_PFC1, sdr0_pfc1);
  91         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
  92                 SDR0_PFC1_SELECT_CONFIG_4;
  93 #ifdef CONFIG_I2C_MULTI_BUS
  94         sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
  95 #endif
  96         mfsdr(SDR0_PFC2, sdr0_pfc2);
  97         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
  98                 SDR0_PFC2_SELECT_CONFIG_4;
  99         mtsdr(SDR0_PFC2, sdr0_pfc2);
 100         mtsdr(SDR0_PFC1, sdr0_pfc1);
 101
 102         /* PCI arbiter enabled */
 103         mfsdr(sdr_pci0, reg);
 104         mtsdr(sdr_pci0, 0x80000000 | reg);
 105
 106         /* setup NAND FLASH */
 107         mfsdr(SDR0_CUST0, sdr0_cust0);
 108         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 109                 SDR0_CUST0_NDFC_ENABLE          |
 110                 SDR0_CUST0_NDFC_BW_8_BIT        |
 111                 SDR0_CUST0_NDFC_ARE_MASK        |
 112                 (0x80000000 >> (28 + CFG_NAND_CS));
 113         mtsdr(SDR0_CUST0, sdr0_cust0);
 114
 115         return 0;
 116 }
 117
 118 int misc_init_r(void)
 119 {
 120         uint pbcr;
 121         int size_val = 0;
 122         u32 reg;
 123 #ifdef CONFIG_440EPX
 124         unsigned long usb2d0cr = 0;
 125         unsigned long usb2phy0cr, usb2h0cr = 0;
 126         unsigned long sdr0_pfc1;
 127         char *act = getenv("usbact");
 128 #endif
 129
 130         /* Re-do flash sizing to get full correct info */
 131
 132         /* adjust flash start and offset */
 133         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 134         gd->bd->bi_flashoffset = 0;
 135
 136 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 137         mtdcr(ebccfga, pb3cr);
 138 #else
 139         mtdcr(ebccfga, pb0cr);
 140 #endif
 141         pbcr = mfdcr(ebccfgd);
 142         size_val = ffs(gd->bd->bi_flashsize) - 21;
 143         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 144 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 145         mtdcr(ebccfga, pb3cr);
 146 #else
 147         mtdcr(ebccfga, pb0cr);
 148 #endif
 149         mtdcr(ebccfgd, pbcr);
 150
 151         /*
 152          * Re-check to get correct base address
 153          */
 154         flash_get_size(gd->bd->bi_flashstart, 0);
 155
 156 #ifdef CFG_ENV_IS_IN_FLASH
 157         /* Monitor protection ON by default */
 158         (void)flash_protect(FLAG_PROTECT_SET,
 159                             -CFG_MONITOR_LEN,
 160                             0xffffffff,
 161                             &flash_info[0]);
 162
 163         /* Env protection ON by default */
 164         (void)flash_protect(FLAG_PROTECT_SET,
 165                             CFG_ENV_ADDR_REDUND,
 166                             CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
 167                             &flash_info[0]);
 168 #endif
 169
 170         /*
 171          * USB suff...
 172          */
 173 #ifdef CONFIG_440EPX
 174         if (act == NULL || strcmp(act, "hostdev") == 0) {
 175                 /* SDR Setting */
 176                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 177                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 178                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 179                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 180
 181                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 182                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 183                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 184                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 185                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 186                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 187                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 188                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 189                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 190                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 191
 192                 /*
 193                  * An 8-bit/60MHz interface is the only possible alternative
 194                  * when connecting the Device to the PHY
 195                  */
 196                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 197                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 198
 199                 /*
 200                  * To enable the USB 2.0 Device function
 201                  * through the UTMI interface
 202                  */
 203                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 204                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
 205
 206                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 207                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
 208
 209                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 210                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 211                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 212                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 213
 214                 /*clear resets*/
 215                 udelay (1000);
 216                 mtsdr(SDR0_SRST1, 0x00000000);
 217                 udelay (1000);
 218                 mtsdr(SDR0_SRST0, 0x00000000);
 219
 220                 printf("USB:   Host(int phy) Device(ext phy)\n");
 221
 222         } else if (strcmp(act, "dev") == 0) {
 223                 /*-------------------PATCH-------------------------------*/
 224                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 225
 226                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 227                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 228                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 229                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 230                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 231                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 232                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 233                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 234                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 235
 236                 udelay (1000);
 237                 mtsdr(SDR0_SRST1, 0x672c6000);
 238
 239                 udelay (1000);
 240                 mtsdr(SDR0_SRST0, 0x00000080);
 241
 242                 udelay (1000);
 243                 mtsdr(SDR0_SRST1, 0x60206000);
 244
 245                 *(unsigned int *)(0xe0000350) = 0x00000001;
 246
 247                 udelay (1000);
 248                 mtsdr(SDR0_SRST1, 0x60306000);
 249                 /*-------------------PATCH-------------------------------*/
 250
 251                 /* SDR Setting */
 252                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 253                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 254                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 255                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 256
 257                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 258                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 259                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 260                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 261                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 262                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 263                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 264                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 265                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 266                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 267
 268                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 269                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 270
 271                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 272                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
 273
 274                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 275                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 276
 277                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 278                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 279                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 280                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 281
 282                 /* clear resets */
 283                 udelay (1000);
 284                 mtsdr(SDR0_SRST1, 0x00000000);
 285                 udelay (1000);
 286                 mtsdr(SDR0_SRST0, 0x00000000);
 287
 288                 printf("USB:   Device(int phy)\n");
 289         }
 290 #endif /* CONFIG_440EPX */
 291
 292         mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
 293         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 294         mtsdr(SDR0_SRST1, reg);
 295
 296         /*
 297          * Clear PLB4A0_ACR[WRP]
 298          * This fix will make the MAL burst disabling patch for the Linux
 299          * EMAC driver obsolete.
 300          */
 301         reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
 302         mtdcr(plb4_acr, reg);
 303
 304         return 0;
 305 }
 306
 307 int checkboard(void)
 308 {
 309         char *s = getenv("serial#");
 310         u8 rev;
 311         u8 val;
 312
 313 #ifdef CONFIG_440EPX
 314         printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 315 #else
 316         printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 317 #endif
 318
 319         rev = in_8((void *)(CFG_BCSR_BASE + 0));
 320         val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
 321         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 322
 323         if (s != NULL) {
 324                 puts(", serial# ");
 325                 puts(s);
 326         }
 327         putc('\n');
 328
 329         return (0);
 330 }
 331
 332 #if defined(CFG_DRAM_TEST)
 333 int testdram(void)
 334 {
 335         unsigned long *mem = (unsigned long *)0;
 336         const unsigned long kend = (1024 / sizeof(unsigned long));
 337         unsigned long k, n;
 338
 339         mtmsr(0);
 340
 341         for (k = 0; k < CFG_MBYTES_SDRAM;
 342              ++k, mem += (1024 / sizeof(unsigned long))) {
 343                 if ((k & 1023) == 0) {
 344                         printf("%3d MB\r", k / 1024);
 345                 }
 346
 347                 memset(mem, 0xaaaaaaaa, 1024);
 348                 for (n = 0; n < kend; ++n) {
 349                         if (mem[n] != 0xaaaaaaaa) {
 350                                 printf("SDRAM test fails at: %08x\n",
 351                                        (uint) & mem[n]);
 352                                 return 1;
 353                         }
 354                 }
 355
 356                 memset(mem, 0x55555555, 1024);
 357                 for (n = 0; n < kend; ++n) {
 358                         if (mem[n] != 0x55555555) {
 359                                 printf("SDRAM test fails at: %08x\n",
 360                                        (uint) & mem[n]);
 361                                 return 1;
 362                         }
 363                 }
 364         }
 365         printf("SDRAM test passes\n");
 366         return 0;
 367 }
 368 #endif
 369
 370 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 371 /*
 372  * Assign interrupts to PCI devices.
 373  */
 374 void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 375 {
 376         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
 377 }
 378 #endif
 379
 380 /*
 381  * pci_pre_init
 382  *
 383  * This routine is called just prior to registering the hose and gives
 384  * the board the opportunity to check things. Returning a value of zero
 385  * indicates that things are bad & PCI initialization should be aborted.
 386  *
 387  * Different boards may wish to customize the pci controller structure
 388  * (add regions, override default access routines, etc) or perform
 389  * certain pre-initialization actions.
 390  */
 391 #if defined(CONFIG_PCI)
 392 int pci_pre_init(struct pci_controller *hose)
 393 {
 394         unsigned long addr;
 395
 396         /*
 397          * Set priority for all PLB3 devices to 0.
 398          * Set PLB3 arbiter to fair mode.
 399          */
 400         mfsdr(sdr_amp1, addr);
 401         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 402         addr = mfdcr(plb3_acr);
 403         mtdcr(plb3_acr, addr | 0x80000000);
 404
 405         /*
 406          * Set priority for all PLB4 devices to 0.
 407          */
 408         mfsdr(sdr_amp0, addr);
 409         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 410         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 411         mtdcr(plb4_acr, addr);
 412
 413         /*
 414          * Set Nebula PLB4 arbiter to fair mode.
 415          */
 416         /* Segment0 */
 417         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 418         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 419         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 420         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 421         mtdcr(plb0_acr, addr);
 422
 423         /* Segment1 */
 424         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 425         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 426         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 427         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 428         mtdcr(plb1_acr, addr);
 429
 430 #ifdef CONFIG_PCI_PNP
 431         hose->fixup_irq = sequoia_pci_fixup_irq;
 432 #endif
 433         return 1;
 434 }
 435 #endif /* defined(CONFIG_PCI) */
 436
 437 /*
 438  * pci_target_init
 439  *
 440  * The bootstrap configuration provides default settings for the pci
 441  * inbound map (PIM). But the bootstrap config choices are limited and
 442  * may not be sufficient for a given board.
 443  */
 444 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 445 void pci_target_init(struct pci_controller *hose)
 446 {
 447         /*
 448          * Set up Direct MMIO registers
 449          */
 450         /*
 451          * PowerPC440EPX PCI Master configuration.
 452          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 453          * PLB address 0xA0000000-0xDFFFFFFF
 454          *     ==> PCI address 0xA0000000-0xDFFFFFFF
 455          * Use byte reversed out routines to handle endianess.
 456          * Make this region non-prefetchable.
 457          */
 458         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
 459                                                 /* - disabled b4 setting */
 460         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 461         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
 462         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 463         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
 464                                                 /* and enable region */
 465
 466         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
 467                                                 /* - disabled b4 setting */
 468         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 469         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
 470         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 471         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
 472                                                 /* and enable region */
 473
 474         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 475         out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
 476         out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
 477         out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
 478
 479         /*
 480          * Set up Configuration registers
 481          */
 482
 483         /* Program the board's subsystem id/vendor id */
 484         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 485                               CFG_PCI_SUBSYS_VENDORID);
 486         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 487
 488         /* Configure command register as bus master */
 489         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 490
 491         /* 240nS PCI clock */
 492         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 493
 494         /* No error reporting */
 495         pci_write_config_word(0, PCI_ERREN, 0);
 496
 497         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 498
 499 }
 500 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 501
 502 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 503 void pci_master_init(struct pci_controller *hose)
 504 {
 505         unsigned short temp_short;
 506
 507         /*
 508          * Write the PowerPC440 EP PCI Configuration regs.
 509          * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 510          * Enable PowerPC440 EP to act as a PCI memory target (PTM).
 511          */
 512         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 513         pci_write_config_word(0, PCI_COMMAND,
 514                               temp_short | PCI_COMMAND_MASTER |
 515                               PCI_COMMAND_MEMORY);
 516 }
 517 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 518
 519 /*
 520  * is_pci_host
 521  *
 522  * This routine is called to determine if a pci scan should be
 523  * performed. With various hardware environments (especially cPCI and
 524  * PPMC) it's insufficient to depend on the state of the arbiter enable
 525  * bit in the strap register, or generic host/adapter assumptions.
 526  *
 527  * Rather than hard-code a bad assumption in the general 440 code, the
 528  * 440 pci code requires the board to decide at runtime.
 529  *
 530  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 531  */
 532 #if defined(CONFIG_PCI)
 533 int is_pci_host(struct pci_controller *hose)
 534 {
 535         /* Cactus is always configured as host. */
 536         return (1);
 537 }
 538 #endif /* defined(CONFIG_PCI) */
 539
 540 #if defined(CONFIG_POST)
 541 /*
 542  * Returns 1 if keys pressed to start the power-on long-running tests
 543  * Called from board_init_f().
 544  */
 545 int post_hotkeys_pressed(void)
 546 {
 547         return 0;       /* No hotkeys supported */
 548 }
 549 #endif /* CONFIG_POST */
 550
 551 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 552 void ft_board_setup(void *blob, bd_t *bd)
 553 {
 554         u32 val[4];
 555         int rc;
 556
 557         ft_cpu_setup(blob, bd);
 558
 559         /* Fixup NOR mapping */
 560         val[0] = 0;                             /* chip select number */
 561         val[1] = 0;                             /* always 0 */
 562         val[2] = gd->bd->bi_flashstart;
 563         val[3] = gd->bd->bi_flashsize;
 564         rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 565                                   val, sizeof(val), 1);
 566         if (rc)
 567                 printf("Unable to update property NOR mapping, err=%s\n",
 568                        fdt_strerror(rc));
 569 }
 570 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */