board/amcc/ebony/ebony.c

   1 /*
   2  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  28 #define FLASH_ONBD_N            2       /* 00000010 */
  29 #define FLASH_SRAM_SEL          1       /* 00000001 */
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 long int fixed_sdram(void);
  34
  35 int board_early_init_f(void)
  36 {
  37         uint reg;
  38         unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
  39         unsigned char status;
  40
  41         /*--------------------------------------------------------------------
  42          * Setup the external bus controller/chip selects
  43          *-------------------------------------------------------------------*/
  44         mtdcr(ebccfga, xbcfg);
  45         reg = mfdcr(ebccfgd);
  46         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  47
  48         mtebc(pb1ap, 0x02815480);       /* NVRAM/RTC */
  49         mtebc(pb1cr, 0x48018000);       /* BA=0x480 1MB R/W 8-bit */
  50         mtebc(pb7ap, 0x01015280);       /* FPGA registers */
  51         mtebc(pb7cr, 0x48318000);       /* BA=0x483 1MB R/W 8-bit */
  52
  53         /* read FPGA_REG0  and set the bus controller */
  54         status = *fpga_base;
  55         if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
  56                 mtebc(pb0ap, 0x9b015480);       /* FLASH/SRAM */
  57                 mtebc(pb0cr, 0xfff18000);       /* BAS=0xfff 1MB R/W 8-bit */
  58                 mtebc(pb2ap, 0x9b015480);       /* 4MB FLASH */
  59                 mtebc(pb2cr, 0xff858000);       /* BAS=0xff8 4MB R/W 8-bit */
  60         } else {
  61                 mtebc(pb0ap, 0x9b015480);       /* 4MB FLASH */
  62                 mtebc(pb0cr, 0xffc58000);       /* BAS=0xffc 4MB R/W 8-bit */
  63
  64                 /* set CS2 if FLASH_ONBD_N == 0 */
  65                 if (!(status & FLASH_ONBD_N)) {
  66                         mtebc(pb2ap, 0x9b015480);       /* FLASH/SRAM */
  67                         mtebc(pb2cr, 0xff818000);       /* BAS=0xff8 4MB R/W 8-bit */
  68                 }
  69         }
  70
  71         /*--------------------------------------------------------------------
  72          * Setup the interrupt controller polarities, triggers, etc.
  73          *-------------------------------------------------------------------*/
  74         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  75         mtdcr(uic0er, 0x00000000);      /* disable all */
  76         mtdcr(uic0cr, 0x00000009);      /* SMI & UIC1 crit are critical */
  77         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
  78         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
  79         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
  80         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  81
  82         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  83         mtdcr(uic1er, 0x00000000);      /* disable all */
  84         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  85         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
  86         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
  87         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
  88         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  89
  90         return 0;
  91 }
  92
  93 int checkboard(void)
  94 {
  95         char *s = getenv("serial#");
  96
  97         printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
  98         if (s != NULL) {
  99                 puts(", serial# ");
 100                 puts(s);
 101         }
 102         putc('\n');
 103
 104         return (0);
 105 }
 106
 107 long int initdram(int board_type)
 108 {
 109         long dram_size = 0;
 110
 111 #if defined(CONFIG_SPD_EEPROM)
 112         dram_size = spd_sdram();
 113 #else
 114         dram_size = fixed_sdram();
 115 #endif
 116         return dram_size;
 117 }
 118
 119 #if defined(CFG_DRAM_TEST)
 120 int testdram(void)
 121 {
 122         uint *pstart = (uint *) 0x00000000;
 123         uint *pend = (uint *) 0x08000000;
 124         uint *p;
 125
 126         for (p = pstart; p < pend; p++)
 127                 *p = 0xaaaaaaaa;
 128
 129         for (p = pstart; p < pend; p++) {
 130                 if (*p != 0xaaaaaaaa) {
 131                         printf("SDRAM test fails at: %08x\n", (uint) p);
 132                         return 1;
 133                 }
 134         }
 135
 136         for (p = pstart; p < pend; p++)
 137                 *p = 0x55555555;
 138
 139         for (p = pstart; p < pend; p++) {
 140                 if (*p != 0x55555555) {
 141                         printf("SDRAM test fails at: %08x\n", (uint) p);
 142                         return 1;
 143                 }
 144         }
 145         return 0;
 146 }
 147 #endif
 148
 149 #if !defined(CONFIG_SPD_EEPROM)
 150 /*************************************************************************
 151  *  fixed sdram init -- doesn't use serial presence detect.
 152  *
 153  *  Assumes:    128 MB, non-ECC, non-registered
 154  *              PLB @ 133 MHz
 155  *
 156  ************************************************************************/
 157 long int fixed_sdram(void)
 158 {
 159         uint reg;
 160
 161         /*--------------------------------------------------------------------
 162          * Setup some default
 163          *------------------------------------------------------------------*/
 164         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 165         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 166         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 167         mtsdram(mem_wddctr, 0x00000000);        /* wrcp=0 dcd=0                 */
 168         mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0    */
 169
 170         /*--------------------------------------------------------------------
 171          * Setup for board-specific specific mem
 172          *------------------------------------------------------------------*/
 173         /*
 174          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 175          */
 176         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 177         mtsdram(mem_tr0, 0x410a4012);   /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 178         /* RA=10 RD=3                       */
 179         mtsdram(mem_tr1, 0x8080082f);   /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 180         mtsdram(mem_rtr, 0x08200000);   /* Rate 15.625 ns @ 133 MHz PLB     */
 181         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 182         udelay(400);            /* Delay 200 usecs (min)            */
 183
 184         /*--------------------------------------------------------------------
 185          * Enable the controller, then wait for DCEN to complete
 186          *------------------------------------------------------------------*/
 187         mtsdram(mem_cfg0, 0x86000000);  /* DCEN=1, PMUD=1, 64-bit           */
 188         for (;;) {
 189                 mfsdram(mem_mcsts, reg);
 190                 if (reg & 0x80000000)
 191                         break;
 192         }
 193
 194         return (128 * 1024 * 1024);     /* 128 MB                           */
 195 }
 196 #endif                          /* !defined(CONFIG_SPD_EEPROM) */
 197
 198 /*************************************************************************
 199  *  pci_pre_init
 200  *
 201  *  This routine is called just prior to registering the hose and gives
 202  *  the board the opportunity to check things. Returning a value of zero
 203  *  indicates that things are bad & PCI initialization should be aborted.
 204  *
 205  *      Different boards may wish to customize the pci controller structure
 206  *      (add regions, override default access routines, etc) or perform
 207  *      certain pre-initialization actions.
 208  *
 209  ************************************************************************/
 210 #if defined(CONFIG_PCI)
 211 int pci_pre_init(struct pci_controller *hose)
 212 {
 213         unsigned long strap;
 214
 215         /*--------------------------------------------------------------------------+
 216          * The ebony board is always configured as the host & requires the
 217          * PCI arbiter to be enabled.
 218          *--------------------------------------------------------------------------*/
 219         strap = mfdcr(cpc0_strp1);
 220         if ((strap & 0x00100000) == 0) {
 221                 printf("PCI: CPC0_STRP1[PAE] not set.\n");
 222                 return 0;
 223         }
 224
 225         return 1;
 226 }
 227 #endif  /* defined(CONFIG_PCI) */
 228
 229 /*************************************************************************
 230  *  pci_target_init
 231  *
 232  *      The bootstrap configuration provides default settings for the pci
 233  *      inbound map (PIM). But the bootstrap config choices are limited and
 234  *      may not be sufficient for a given board.
 235  *
 236  ************************************************************************/
 237 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 238 void pci_target_init(struct pci_controller *hose)
 239 {
 240         /*--------------------------------------------------------------------------+
 241          * Disable everything
 242          *--------------------------------------------------------------------------*/
 243         out32r(PCIX0_PIM0SA, 0);        /* disable */
 244         out32r(PCIX0_PIM1SA, 0);        /* disable */
 245         out32r(PCIX0_PIM2SA, 0);        /* disable */
 246         out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
 247
 248         /*--------------------------------------------------------------------------+
 249          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 250      * options to not support sizes such as 128/256 MB.
 251          *--------------------------------------------------------------------------*/
 252         out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
 253         out32r(PCIX0_PIM0LAH, 0);
 254         out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 255
 256         out32r(PCIX0_BAR0, 0);
 257
 258         /*--------------------------------------------------------------------------+
 259          * Program the board's subsystem id/vendor id
 260          *--------------------------------------------------------------------------*/
 261         out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
 262         out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
 263
 264         out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 265 }
 266 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 267
 268 /*************************************************************************
 269  *  is_pci_host
 270  *
 271  *      This routine is called to determine if a pci scan should be
 272  *      performed. With various hardware environments (especially cPCI and
 273  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 274  *      bit in the strap register, or generic host/adapter assumptions.
 275  *
 276  *      Rather than hard-code a bad assumption in the general 440 code, the
 277  *      440 pci code requires the board to decide at runtime.
 278  *
 279  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 280  *
 281  *
 282  ************************************************************************/
 283 #if defined(CONFIG_PCI)
 284 int is_pci_host(struct pci_controller *hose)
 285 {
 286         /* The ebony board is always configured as host. */
 287         return (1);
 288 }
 289 #endif                          /* defined(CONFIG_PCI) */