board/ads5121/pci.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24
  25 #include <asm/mmu.h>
  26 #include <asm/global_data.h>
  27 #include <pci.h>
  28 #if defined(CONFIG_OF_LIBFDT)
  29 #include <libfdt.h>
  30 #include <fdt_support.h>
  31 #endif
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* System RAM mapped to PCI space */
  36 #define CONFIG_PCI_SYS_MEM_BUS  CFG_SDRAM_BASE
  37 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
  38
  39 static struct pci_controller pci_hose;
  40
  41
  42 /**************************************************************************
  43  * pci_init_board()
  44  *
  45  */
  46 void
  47 pci_init_board(void)
  48 {
  49         volatile immap_t *immr = (immap_t *) CFG_IMMR;
  50         volatile law512x_t *pci_law;
  51         volatile pot512x_t *pci_pot;
  52         volatile pcictrl512x_t *pci_ctrl;
  53         volatile pciconf512x_t *pci_conf;
  54         u16 reg16;
  55         u32 reg32;
  56         u32 dev;
  57         struct pci_controller *hose;
  58
  59         /* Set PCI divider for 33MHz */
  60         reg32 = immr->clk.scfr[0];
  61         reg32 &= ~(SCFR1_PCI_DIV_MASK);
  62         reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
  63         immr->clk.scfr[0] = reg32;
  64
  65         pci_law = immr->sysconf.pcilaw;
  66         pci_pot = immr->ios.pot;
  67         pci_ctrl = &immr->pci_ctrl;
  68         pci_conf = &immr->pci_conf;
  69
  70         hose = &pci_hose;
  71
  72         /*
  73          * Release PCI RST Output signal
  74          */
  75         pci_ctrl->gcr = 0;
  76         udelay(2000);
  77         pci_ctrl->gcr = 1;
  78
  79         /* We need to wait at least a 1sec based on PCI specs */
  80         {
  81                 int i;
  82
  83                 for (i = 0; i < 1000; i++)
  84                         udelay(1000);
  85         }
  86
  87         /*
  88          * Configure PCI Local Access Windows
  89          */
  90         pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
  91         pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
  92
  93         pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
  94         pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
  95
  96         /*
  97          * Configure PCI Outbound Translation Windows
  98          */
  99
 100         /* PCI mem space - prefetch */
 101         pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
 102         pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
 103         pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
 104
 105         /* PCI IO space */
 106         pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
 107         pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
 108         pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
 109
 110         /* PCI mmio - non-prefetch mem space */
 111         pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
 112         pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 113         pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
 114
 115         /*
 116          * Configure PCI Inbound Translation Windows
 117          */
 118
 119         /* we need RAM mapped to PCI space for the devices to
 120          * access main memory */
 121         pci_ctrl[0].pitar1 = 0x0;
 122         pci_ctrl[0].pibar1 = 0x0;
 123         pci_ctrl[0].piebar1 = 0x0;
 124         pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 125             PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
 126
 127         hose->first_busno = 0;
 128         hose->last_busno = 0xff;
 129
 130         /* PCI memory prefetch space */
 131         pci_set_region(hose->regions + 0,
 132                        CFG_PCI_MEM_BASE,
 133                        CFG_PCI_MEM_PHYS,
 134                        CFG_PCI_MEM_SIZE,
 135                        PCI_REGION_MEM|PCI_REGION_PREFETCH);
 136
 137         /* PCI memory space */
 138         pci_set_region(hose->regions + 1,
 139                        CFG_PCI_MMIO_BASE,
 140                        CFG_PCI_MMIO_PHYS,
 141                        CFG_PCI_MMIO_SIZE,
 142                        PCI_REGION_MEM);
 143
 144         /* PCI IO space */
 145         pci_set_region(hose->regions + 2,
 146                        CFG_PCI_IO_BASE,
 147                        CFG_PCI_IO_PHYS,
 148                        CFG_PCI_IO_SIZE,
 149                        PCI_REGION_IO);
 150
 151         /* System memory space */
 152         pci_set_region(hose->regions + 3,
 153                        CONFIG_PCI_SYS_MEM_BUS,
 154                        CONFIG_PCI_SYS_MEM_PHYS,
 155                        gd->ram_size,
 156                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 157
 158         hose->region_count = 4;
 159
 160         pci_setup_indirect(hose,
 161                            (CFG_IMMR + 0x8300),
 162                            (CFG_IMMR + 0x8304));
 163
 164         pci_register_hose(hose);
 165
 166         /*
 167          * Write to Command register
 168          */
 169         reg16 = 0xff;
 170         dev = PCI_BDF(hose->first_busno, 0, 0);
 171         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
 172         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 173         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 174
 175         /*
 176          * Clear non-reserved bits in status register.
 177          */
 178         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 179         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 180         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 181
 182 #ifdef CONFIG_PCI_SCAN_SHOW
 183         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 184 #endif
 185         /*
 186          * Hose scan.
 187          */
 188         hose->last_busno = pci_hose_scan(hose);
 189 }
 190
 191 #if defined(CONFIG_OF_LIBFDT)
 192 void ft_pci_setup(void *blob, bd_t *bd)
 193 {
 194         int nodeoffset;
 195         int tmp[2];
 196         const char *path;
 197
 198         nodeoffset = fdt_path_offset(blob, "/aliases");
 199         if (nodeoffset >= 0) {
 200                 path = fdt_getprop(blob, nodeoffset, "pci", NULL);
 201                 if (path) {
 202                         tmp[0] = cpu_to_be32(pci_hose.first_busno);
 203                         tmp[1] = cpu_to_be32(pci_hose.last_busno);
 204                         do_fixup_by_path(blob, path, "bus-range",
 205                                 &tmp, sizeof(tmp), 1);
 206
 207                         tmp[0] = cpu_to_be32(gd->pci_clk);
 208                         do_fixup_by_path(blob, path, "clock-frequency",
 209                                 &tmp, sizeof(tmp[0]), 1);
 210                 }
 211         }
 212 }
 213 #endif /* CONFIG_OF_LIBFDT */