2 * i2c.c - driver for Blackfin on-chip TWI/I2C
4 * Copyright (c) 2006-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
11 #ifdef CONFIG_HARD_I2C
13 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/twi.h>
18 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
20 #define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV()
21 #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
22 #define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL()
23 #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
24 #define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL()
25 #define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val)
26 #define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT()
27 #define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val)
28 #define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR()
29 #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val)
30 #define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL()
31 #define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val)
32 #define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT()
33 #define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val)
34 #define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR()
35 #define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
36 #define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT()
37 #define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val)
38 #define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK()
39 #define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val)
40 #define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL()
41 #define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val)
42 #define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT()
43 #define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val)
44 #define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8()
45 #define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val)
46 #define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16()
47 #define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val)
48 #define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8()
49 #define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val)
50 #define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16()
51 #define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val)
55 #define PRINTD(fmt,args...) do { \
56 DECLARE_GLOBAL_DATA_PTR; \
57 if (gd->have_console) \
58 printf(fmt ,##args); \
61 #define PRINTD(fmt,args...)
64 #ifndef CONFIG_TWICLK_KHZ
65 #define CONFIG_TWICLK_KHZ 50
68 /* All transfers are described by this data structure */
70 u16 addr
; /* slave address */
72 #define I2C_M_STOP 0x2
74 u16 len
; /* msg length */
75 u8
*buf
; /* pointer to msg data */
79 * i2c_reset: - reset the host controller
81 static void i2c_reset(void)
84 bfin_write_TWI_CONTROL(0);
87 /* Set TWI internal clock as 10MHz */
88 bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
90 /* Set Twi interface clock as specified */
91 if (CONFIG_TWICLK_KHZ
> 400)
92 bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
95 bfin_write_TWI_CLKDIV(((5 * 1024 /
96 CONFIG_TWICLK_KHZ
) << 8) | ((5 * 1024 /
101 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA
);
105 int wait_for_completion(struct i2c_msg
*msg
, int timeout_count
)
107 unsigned short twi_int_stat
;
108 unsigned short mast_stat
;
111 for (i
= 0; i
< timeout_count
; i
++) {
112 twi_int_stat
= bfin_read_TWI_INT_STAT();
113 mast_stat
= bfin_read_TWI_MASTER_STAT();
115 if (XMTSERV
& twi_int_stat
) {
116 /* Transmit next data */
118 bfin_write_TWI_XMT_DATA8(*(msg
->buf
++));
120 } else if (msg
->flags
& I2C_M_STOP
)
121 bfin_write_TWI_MASTER_CTL
122 (bfin_read_TWI_MASTER_CTL() | STOP
);
125 bfin_write_TWI_INT_STAT(XMTSERV
);
129 if (RCVSERV
& twi_int_stat
) {
131 /* Receive next data */
132 *(msg
->buf
++) = bfin_read_TWI_RCV_DATA8();
134 } else if (msg
->flags
& I2C_M_STOP
) {
135 bfin_write_TWI_MASTER_CTL
136 (bfin_read_TWI_MASTER_CTL() | STOP
);
139 /* Clear interrupt source */
140 bfin_write_TWI_INT_STAT(RCVSERV
);
144 if (MERR
& twi_int_stat
) {
145 bfin_write_TWI_INT_STAT(MERR
);
146 bfin_write_TWI_INT_MASK(0);
147 bfin_write_TWI_MASTER_STAT(0x3e);
148 bfin_write_TWI_MASTER_CTL(0);
151 * if both err and complete int stats are set,
152 * return proper results.
154 if (MCOMP
& twi_int_stat
) {
155 bfin_write_TWI_INT_STAT(MCOMP
);
156 bfin_write_TWI_INT_MASK(0);
157 bfin_write_TWI_MASTER_CTL(0);
160 * If it is a quick transfer,
161 * only address bug no data, not an err.
163 if (msg
->len
== 0 && mast_stat
& BUFRDERR
)
166 * If address not acknowledged return -3,
169 else if (!(mast_stat
& ANAK
))
176 if (MCOMP
& twi_int_stat
) {
177 bfin_write_TWI_INT_STAT(MCOMP
);
179 bfin_write_TWI_INT_MASK(0);
180 bfin_write_TWI_MASTER_CTL(0);
185 if (msg
->flags
& I2C_M_RD
)
192 * i2c_transfer: - Transfer one byte over the i2c bus
194 * This function can tranfer a byte over the i2c bus in both directions.
195 * It is used by the public API functions.
197 * @return: 0: transfer successful
199 * -2: transmit timeout
201 * -4: receive timeout
202 * -5: controller not ready
204 int i2c_transfer(struct i2c_msg
*msg
)
207 int timeout_count
= 10000;
210 if (!(bfin_read_TWI_CONTROL() & TWI_ENA
)) {
215 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY
)
218 /* Set Transmit device address */
219 bfin_write_TWI_MASTER_ADDR(msg
->addr
);
223 * Data in FIFO should be discarded before start a new operation.
225 bfin_write_TWI_FIFO_CTL(0x3);
227 bfin_write_TWI_FIFO_CTL(0);
230 if (!(msg
->flags
& I2C_M_RD
)) {
231 /* Transmit first data */
233 PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg
->buf
,
235 bfin_write_TWI_XMT_DATA8(*(msg
->buf
++));
242 bfin_write_TWI_INT_STAT(MERR
| MCOMP
| XMTSERV
| RCVSERV
);
244 /* Interrupt mask . Enable XMT, RCV interrupt */
245 bfin_write_TWI_INT_MASK(MCOMP
| MERR
|
246 ((msg
->flags
& I2C_M_RD
) ? RCVSERV
: XMTSERV
));
249 if (len
> 0 && len
<= 255)
250 bfin_write_TWI_MASTER_CTL((len
<< 6));
251 else if (msg
->len
> 255) {
252 bfin_write_TWI_MASTER_CTL((0xff << 6));
253 msg
->flags
&= I2C_M_STOP
;
255 bfin_write_TWI_MASTER_CTL(0);
258 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN
|
259 ((msg
->flags
& I2C_M_RD
)
260 ? MDIR
: 0) | ((CONFIG_TWICLK_KHZ
>
264 ret
= wait_for_completion(msg
, timeout_count
);
265 PRINTD("3 in i2c_transfer: ret=%d\n", ret
);
270 PRINTD(("i2c_transfer: error: transfer fail\n"));
273 PRINTD(("i2c_transfer: error: transmit timeout\n"));
276 PRINTD(("i2c_transfer: error: ACK missing\n"));
279 PRINTD(("i2c_transfer: error: receive timeout\n"));
282 PRINTD(("i2c_transfer: error: controller not ready\n"));
292 /* ---------------------------------------------------------------------*/
294 /* ---------------------------------------------------------------------*/
296 void i2c_init(int speed
, int slaveaddr
)
302 * i2c_probe: - Test if a chip answers for a given i2c address
304 * @chip: address of the chip which is searched for
305 * @return: 0 if a chip was found, -1 otherwhise
308 int i2c_probe(uchar chip
)
320 if (i2c_transfer(&msg
))
324 msg
.flags
= I2C_M_RD
;
327 if (i2c_transfer(&msg
))
334 * i2c_read: - Read multiple bytes from an i2c device
336 * chip: I2C chip address, range 0..127
337 * addr: Memory (register) address within the chip
338 * alen: Number of bytes to use for addr (typically 1, 2 for larger
339 * memories, 0 for register type devices with only one
341 * buffer: Where to read/write the data
342 * len: How many bytes to read/write
344 * Returns: 0 on success, not 0 on failure
347 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
* buffer
, int len
)
350 u8 addr_bytes
[3]; /* lowest...highest byte of data address */
352 PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip
,
356 addr_bytes
[0] = (u8
) ((addr
>> 0) & 0x000000FF);
357 addr_bytes
[1] = (u8
) ((addr
>> 8) & 0x000000FF);
358 addr_bytes
[2] = (u8
) ((addr
>> 16) & 0x000000FF);
362 msg
.buf
= addr_bytes
;
363 if (i2c_transfer(&msg
))
367 /* start read sequence */
368 PRINTD(("i2c_read: start read sequence\n"));
370 msg
.flags
= I2C_M_RD
;
373 if (i2c_transfer(&msg
))
380 * i2c_write: - Write multiple bytes to an i2c device
382 * chip: I2C chip address, range 0..127
383 * addr: Memory (register) address within the chip
384 * alen: Number of bytes to use for addr (typically 1, 2 for larger
385 * memories, 0 for register type devices with only one
387 * buffer: Where to read/write the data
388 * len: How many bytes to read/write
390 * Returns: 0 on success, not 0 on failure
393 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
* buffer
, int len
)
396 u8 addr_bytes
[3]; /* lowest...highest byte of data address */
399 ("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
400 chip
, addr
, alen
, len
, buffer
[0]);
402 /* chip address write */
404 addr_bytes
[0] = (u8
) ((addr
>> 0) & 0x000000FF);
405 addr_bytes
[1] = (u8
) ((addr
>> 8) & 0x000000FF);
406 addr_bytes
[2] = (u8
) ((addr
>> 16) & 0x000000FF);
410 msg
.buf
= addr_bytes
;
411 if (i2c_transfer(&msg
))
415 /* start read sequence */
416 PRINTD(("i2c_write: start write sequence\n"));
421 if (i2c_transfer(&msg
))
428 uchar
i2c_reg_read(uchar chip
, uchar reg
)
432 PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip
, reg
);
433 i2c_read(chip
, reg
, 0, &buf
, 1);
437 void i2c_reg_write(uchar chip
, uchar reg
, uchar val
)
439 PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip
,
441 i2c_write(chip
, reg
, 0, &val
, 1);
444 #endif /* CONFIG_HARD_I2C */