3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Back ported to the 8xx platform (from the 8260 platform) by
27 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
32 #ifdef CONFIG_HARD_I2C
40 DECLARE_GLOBAL_DATA_PTR
;
42 /* define to enable debug messages */
45 /*-----------------------------------------------------------------------
49 #define CFG_I2C_SPEED 50000
53 #define CFG_I2C_SLAVE 0xFE
55 /*-----------------------------------------------------------------------
58 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
59 #define TOUT_LOOP 1000000
63 #define MAX_TX_SPACE 256
64 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
68 unsigned short status
;
69 unsigned short length
;
72 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
74 #define BD_I2C_TX_CL 0x0001 /* collision error */
75 #define BD_I2C_TX_UN 0x0002 /* underflow error */
76 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
77 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
79 #define BD_I2C_RX_ERR BD_SC_OV
81 typedef void (*i2c_ecb_t
)(int, int); /* error callback function */
83 /* This structure keeps track of the bd and buffer space usage. */
84 typedef struct i2c_state
{
85 int rx_idx
; /* index to next free Rx BD */
86 int tx_idx
; /* index to next free Tx BD */
87 void *rxbd
; /* pointer to next free Rx BD */
88 void *txbd
; /* pointer to next free Tx BD */
89 int tx_space
; /* number of Tx bytes left */
90 unsigned char *tx_buf
; /* pointer to free Tx area */
91 i2c_ecb_t err_cb
; /* error callback function */
95 /* flags for i2c_send() and i2c_receive() */
96 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
97 #define I2CF_START_COND 0x02 /* tx: generate start condition */
98 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
101 #define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
102 #define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
103 #define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
104 #define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
106 /* error callback flags */
107 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
108 #define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
109 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
110 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
111 #define I2CECB_TX_CL 0x01 /* transmit collision error */
112 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
113 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
114 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
115 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
118 #define PRINTD(x) printf x
124 * Returns the best value of I2BRG to meet desired clock speed of I2C with
125 * input parameters (clock speed, filter, and predivider value).
126 * It returns computer speed value and the difference between it and desired
130 i2c_roundrate(int hz
, int speed
, int filter
, int modval
,
131 int *brgval
, int *totspeed
)
133 int moddiv
= 1 << (5-(modval
& 3)), brgdiv
, div
;
135 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
136 hz
, speed
, filter
, modval
));
138 div
= moddiv
* speed
;
139 brgdiv
= (hz
+ div
- 1) / div
;
141 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv
, brgdiv
));
143 *brgval
= ((brgdiv
+ 1) / 2) - 3 - (2*filter
);
145 if ((*brgval
< 0) || (*brgval
> 255)) {
146 PRINTD(("\t\trejected brgval=%d\n", *brgval
));
150 brgdiv
= 2 * (*brgval
+ 3 + (2 * filter
));
151 div
= moddiv
* brgdiv
;
152 *totspeed
= hz
/ div
;
154 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval
, *totspeed
));
160 * Sets the I2C clock predivider and divider to meet required clock speed.
163 i2c_setrate (int hz
, int speed
)
165 immap_t
*immap
= (immap_t
*) CFG_IMMR
;
166 volatile i2c8xx_t
*i2c
= (i2c8xx_t
*) & immap
->im_i2c
;
169 bestspeed_diff
= speed
,
170 bestspeed_brgval
= 0,
171 bestspeed_modval
= 0,
172 bestspeed_filter
= 0,
174 filter
= 0; /* Use this fixed value */
176 for (modval
= 0; modval
< 4; modval
++) {
177 if (i2c_roundrate(hz
,speed
,filter
,modval
,&brgval
,&totspeed
) == 0) {
178 int diff
= speed
- totspeed
;
180 if ((diff
>= 0) && (diff
< bestspeed_diff
)) {
181 bestspeed_diff
= diff
;
182 bestspeed_modval
= modval
;
183 bestspeed_brgval
= brgval
;
184 bestspeed_filter
= filter
;
189 PRINTD (("[I2C] Best is:\n"));
190 PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
198 i2c
->i2c_i2mod
|= ((bestspeed_modval
& 3) << 1) | (bestspeed_filter
<< 3);
199 i2c
->i2c_i2brg
= bestspeed_brgval
& 0xff;
201 PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c
->i2c_i2mod
,
208 i2c_init(int speed
, int slaveaddr
)
210 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
211 volatile cpm8xx_t
*cp
= (cpm8xx_t
*)&immap
->im_cpm
;
212 volatile i2c8xx_t
*i2c
= (i2c8xx_t
*)&immap
->im_i2c
;
213 volatile iic_t
*iip
= (iic_t
*)&cp
->cp_dparam
[PROFF_IIC
];
215 volatile I2C_BD
*rxbd
, *txbd
;
218 #ifdef CFG_I2C_INIT_BOARD
219 /* call board specific i2c bus reset routine before accessing the */
220 /* environment, which might be in a chip on that bus. For details */
221 /* about this problem see doc/I2C_Edge_Conditions. */
225 #ifdef CFG_I2C_UCODE_PATCH
226 iip
= (iic_t
*)&cp
->cp_dpmem
[iip
->iic_rpbase
];
228 /* Disable relocation */
232 #ifdef CFG_ALLOC_DPRAM
233 dpaddr
= iip
->iic_rbase
;
235 /* need to allocate dual port ram */
236 dpaddr
= dpram_alloc_align(
237 (NUM_RX_BDS
* sizeof(I2C_BD
)) + (NUM_TX_BDS
* sizeof(I2C_BD
)) +
241 dpaddr
= CPM_I2C_BASE
;
245 * initialise data in dual port ram:
247 * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
248 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
249 * tx buffer (MAX_TX_SPACE bytes)
253 tbase
= rbase
+ NUM_RX_BDS
* sizeof(I2C_BD
);
255 /* Initialize Port B I2C pins. */
256 cp
->cp_pbpar
|= 0x00000030;
257 cp
->cp_pbdir
|= 0x00000030;
258 cp
->cp_pbodr
|= 0x00000030;
260 /* Disable interrupts */
261 i2c
->i2c_i2mod
= 0x00;
262 i2c
->i2c_i2cmr
= 0x00;
263 i2c
->i2c_i2cer
= 0xff;
264 i2c
->i2c_i2add
= slaveaddr
;
267 * Set the I2C BRG Clock division factor from desired i2c rate
268 * and current CPU rate (we assume sccr dfbgr field is 0;
269 * divide BRGCLK by 1)
271 PRINTD(("[I2C] Setting rate...\n"));
272 i2c_setrate (gd
->cpu_clk
, CFG_I2C_SPEED
) ;
274 /* Set I2C controller in master mode */
275 i2c
->i2c_i2com
= 0x01;
277 /* Set SDMA bus arbitration level to 5 (SDCR) */
278 immap
->im_siu_conf
.sc_sdcr
= 0x0001 ;
280 /* Initialize Tx/Rx parameters */
281 iip
->iic_rbase
= rbase
;
282 iip
->iic_tbase
= tbase
;
283 rxbd
= (I2C_BD
*)((unsigned char *)&cp
->cp_dpmem
[iip
->iic_rbase
]);
284 txbd
= (I2C_BD
*)((unsigned char *)&cp
->cp_dpmem
[iip
->iic_tbase
]);
286 PRINTD(("[I2C] rbase = %04x\n", iip
->iic_rbase
));
287 PRINTD(("[I2C] tbase = %04x\n", iip
->iic_tbase
));
288 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd
));
289 PRINTD(("[I2C] txbd = %08x\n", (int)txbd
));
291 /* Set big endian byte order */
292 iip
->iic_tfcr
= 0x10;
293 iip
->iic_rfcr
= 0x10;
295 /* Set maximum receive size. */
296 iip
->iic_mrblr
= I2C_RXTX_LEN
;
298 #ifdef CFG_I2C_UCODE_PATCH
300 * Initialize required parameters if using microcode patch.
302 iip
->iic_rbptr
= iip
->iic_rbase
;
303 iip
->iic_tbptr
= iip
->iic_tbase
;
307 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_I2C
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
309 __asm__
__volatile__ ("eieio");
310 } while (cp
->cp_cpcr
& CPM_CR_FLG
);
313 /* Clear events and interrupts */
314 i2c
->i2c_i2cer
= 0xff;
315 i2c
->i2c_i2cmr
= 0x00;
319 i2c_newio(i2c_state_t
*state
)
321 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
322 volatile cpm8xx_t
*cp
= (cpm8xx_t
*)&immap
->im_cpm
;
323 volatile iic_t
*iip
= (iic_t
*)&cp
->cp_dparam
[PROFF_IIC
];
325 PRINTD(("[I2C] i2c_newio\n"));
327 #ifdef CFG_I2C_UCODE_PATCH
328 iip
= (iic_t
*)&cp
->cp_dpmem
[iip
->iic_rpbase
];
332 state
->rxbd
= (void*)&cp
->cp_dpmem
[iip
->iic_rbase
];
333 state
->txbd
= (void*)&cp
->cp_dpmem
[iip
->iic_tbase
];
334 state
->tx_space
= MAX_TX_SPACE
;
335 state
->tx_buf
= (uchar
*)state
->txbd
+ NUM_TX_BDS
* sizeof(I2C_BD
);
336 state
->err_cb
= NULL
;
338 PRINTD(("[I2C] rxbd = %08x\n", (int)state
->rxbd
));
339 PRINTD(("[I2C] txbd = %08x\n", (int)state
->txbd
));
340 PRINTD(("[I2C] tx_buf = %08x\n", (int)state
->tx_buf
));
342 /* clear the buffer memory */
343 memset((char *)state
->tx_buf
, 0, MAX_TX_SPACE
);
347 i2c_send(i2c_state_t
*state
,
348 unsigned char address
,
349 unsigned char secondary_address
,
352 unsigned char *dataout
)
354 volatile I2C_BD
*txbd
;
357 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
358 address
, secondary_address
, flags
, size
));
360 /* trying to send message larger than BD */
361 if (size
> I2C_RXTX_LEN
)
362 return I2CERR_MSG_TOO_LONG
;
364 /* no more free bds */
365 if (state
->tx_idx
>= NUM_TX_BDS
|| state
->tx_space
< (2 + size
))
366 return I2CERR_NO_BUFFERS
;
368 txbd
= (I2C_BD
*)state
->txbd
;
369 txbd
->addr
= state
->tx_buf
;
371 PRINTD(("[I2C] txbd = %08x\n", (int)txbd
));
373 if (flags
& I2CF_START_COND
) {
374 PRINTD(("[I2C] Formatting addresses...\n"));
375 if (flags
& I2CF_ENABLE_SECONDARY
) {
376 txbd
->length
= size
+ 2; /* Length of msg + dest addr */
377 txbd
->addr
[0] = address
<< 1;
378 txbd
->addr
[1] = secondary_address
;
381 txbd
->length
= size
+ 1; /* Length of msg + dest addr */
382 txbd
->addr
[0] = address
<< 1; /* Write dest addr to BD */
386 txbd
->length
= size
; /* Length of message */
391 txbd
->status
= BD_SC_READY
;
392 if (flags
& I2CF_START_COND
)
393 txbd
->status
|= BD_I2C_TX_START
;
394 if (flags
& I2CF_STOP_COND
)
395 txbd
->status
|= BD_SC_LAST
| BD_SC_WRAP
;
397 /* Copy data to send into buffer */
398 PRINTD(("[I2C] copy data...\n"));
399 for(j
= 0; j
< size
; i
++, j
++)
400 txbd
->addr
[i
] = dataout
[j
];
402 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
409 state
->tx_buf
+= txbd
->length
;
410 state
->tx_space
-= txbd
->length
;
412 state
->txbd
= (void*)(txbd
+ 1);
418 i2c_receive(i2c_state_t
*state
,
419 unsigned char address
,
420 unsigned char secondary_address
,
422 unsigned short size_to_expect
,
423 unsigned char *datain
)
425 volatile I2C_BD
*rxbd
, *txbd
;
427 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address
, secondary_address
, flags
));
429 /* Expected to receive too much */
430 if (size_to_expect
> I2C_RXTX_LEN
)
431 return I2CERR_MSG_TOO_LONG
;
433 /* no more free bds */
434 if (state
->tx_idx
>= NUM_TX_BDS
|| state
->rx_idx
>= NUM_RX_BDS
435 || state
->tx_space
< 2)
436 return I2CERR_NO_BUFFERS
;
438 rxbd
= (I2C_BD
*)state
->rxbd
;
439 txbd
= (I2C_BD
*)state
->txbd
;
441 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd
));
442 PRINTD(("[I2C] txbd = %08x\n", (int)txbd
));
444 txbd
->addr
= state
->tx_buf
;
446 /* set up TXBD for destination address */
447 if (flags
& I2CF_ENABLE_SECONDARY
) {
449 txbd
->addr
[0] = address
<< 1; /* Write data */
450 txbd
->addr
[1] = secondary_address
; /* Internal address */
451 txbd
->status
= BD_SC_READY
;
453 txbd
->length
= 1 + size_to_expect
;
454 txbd
->addr
[0] = (address
<< 1) | 0x01;
455 txbd
->status
= BD_SC_READY
;
456 memset(&txbd
->addr
[1], 0, txbd
->length
);
459 /* set up rxbd for reception */
460 rxbd
->status
= BD_SC_EMPTY
;
461 rxbd
->length
= size_to_expect
;
464 txbd
->status
|= BD_I2C_TX_START
;
465 if (flags
& I2CF_STOP_COND
) {
466 txbd
->status
|= BD_SC_LAST
| BD_SC_WRAP
;
467 rxbd
->status
|= BD_SC_WRAP
;
470 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
475 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
482 state
->tx_buf
+= txbd
->length
;
483 state
->tx_space
-= txbd
->length
;
485 state
->txbd
= (void*)(txbd
+ 1);
487 state
->rxbd
= (void*)(rxbd
+ 1);
493 static int i2c_doio(i2c_state_t
*state
)
495 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
496 volatile cpm8xx_t
*cp
= (cpm8xx_t
*)&immap
->im_cpm
;
497 volatile i2c8xx_t
*i2c
= (i2c8xx_t
*)&immap
->im_i2c
;
498 volatile iic_t
*iip
= (iic_t
*)&cp
->cp_dparam
[PROFF_IIC
];
499 volatile I2C_BD
*txbd
, *rxbd
;
502 PRINTD(("[I2C] i2c_doio\n"));
504 #ifdef CFG_I2C_UCODE_PATCH
505 iip
= (iic_t
*)&cp
->cp_dpmem
[iip
->iic_rpbase
];
508 if (state
->tx_idx
<= 0 && state
->rx_idx
<= 0) {
509 PRINTD(("[I2C] No I/O is queued\n"));
510 return I2CERR_QUEUE_EMPTY
;
513 iip
->iic_rbptr
= iip
->iic_rbase
;
514 iip
->iic_tbptr
= iip
->iic_tbase
;
517 PRINTD(("[I2C] Enabling I2C...\n"));
518 i2c
->i2c_i2mod
|= 0x01;
520 /* Begin transmission */
521 i2c
->i2c_i2com
|= 0x80;
523 /* Loop until transmit & receive completed */
525 if (state
->tx_idx
> 0) {
526 txbd
= ((I2C_BD
*)state
->txbd
) - 1;
527 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong
)txbd
));
528 while((txbd
->status
& BD_SC_READY
) && (j
++ < TOUT_LOOP
)) {
532 __asm__
__volatile__ ("eieio");
536 if ((state
->rx_idx
> 0) && (j
< TOUT_LOOP
)) {
537 rxbd
= ((I2C_BD
*)state
->rxbd
) - 1;
538 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong
)rxbd
));
539 while((rxbd
->status
& BD_SC_EMPTY
) && (j
++ < TOUT_LOOP
)) {
543 __asm__
__volatile__ ("eieio");
548 i2c
->i2c_i2mod
&= ~0x01;
550 if (state
->err_cb
!= NULL
) {
554 * if we have an error callback function, look at the
555 * error bits in the bd status and pass them back
558 if ((n
= state
->tx_idx
) > 0) {
559 for (i
= 0; i
< n
; i
++) {
560 txbd
= ((I2C_BD
*)state
->txbd
) - (n
- i
);
561 if ((b
= txbd
->status
& BD_I2C_TX_ERR
) != 0)
562 (*state
->err_cb
)(I2CECB_TX_ERR
|b
, i
);
566 if ((n
= state
->rx_idx
) > 0) {
567 for (i
= 0; i
< n
; i
++) {
568 rxbd
= ((I2C_BD
*)state
->rxbd
) - (n
- i
);
569 if ((b
= rxbd
->status
& BD_I2C_RX_ERR
) != 0)
570 (*state
->err_cb
)(I2CECB_RX_ERR
|b
, i
);
575 (*state
->err_cb
)(I2CECB_TIMEOUT
, 0);
578 return (j
>= TOUT_LOOP
) ? I2CERR_TIMEOUT
: 0;
581 static int had_tx_nak
;
584 i2c_test_callback(int flags
, int xnum
)
586 if ((flags
& I2CECB_TX_ERR
) && (flags
& I2CECB_TX_NAK
))
590 int i2c_probe(uchar chip
)
596 i2c_init(CFG_I2C_SPEED
, CFG_I2C_SLAVE
);
600 state
.err_cb
= i2c_test_callback
;
603 rc
= i2c_receive(&state
, chip
, 0, I2CF_START_COND
|I2CF_STOP_COND
, 1, buf
);
608 rc
= i2c_doio(&state
);
610 if ((rc
!= 0) && (rc
!= I2CERR_TIMEOUT
))
616 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
626 xaddr
[0] = (addr
>> 24) & 0xFF;
627 xaddr
[1] = (addr
>> 16) & 0xFF;
628 xaddr
[2] = (addr
>> 8) & 0xFF;
629 xaddr
[3] = addr
& 0xFF;
631 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
633 * EEPROM chips that implement "address overflow" are ones like
634 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
635 * extra bits end up in the "chip address" bit slots. This makes
636 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
638 * Note that we consider the length of the address field to still
639 * be one byte because the extra address bits are hidden in the
642 chip
|= ((addr
>> (alen
* 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW
);
647 rc
= i2c_send(&state
, chip
, 0, I2CF_START_COND
, alen
, &xaddr
[4-alen
]);
649 if (gd
->have_console
)
650 printf("i2c_read: i2c_send failed (%d)\n", rc
);
654 rc
= i2c_receive(&state
, chip
, 0, I2CF_STOP_COND
, len
, buffer
);
656 if (gd
->have_console
)
657 printf("i2c_read: i2c_receive failed (%d)\n", rc
);
661 rc
= i2c_doio(&state
);
663 if (gd
->have_console
)
664 printf("i2c_read: i2c_doio failed (%d)\n", rc
);
670 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
676 xaddr
[0] = (addr
>> 24) & 0xFF;
677 xaddr
[1] = (addr
>> 16) & 0xFF;
678 xaddr
[2] = (addr
>> 8) & 0xFF;
679 xaddr
[3] = addr
& 0xFF;
681 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
683 * EEPROM chips that implement "address overflow" are ones like
684 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
685 * extra bits end up in the "chip address" bit slots. This makes
686 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
688 * Note that we consider the length of the address field to still
689 * be one byte because the extra address bits are hidden in the
692 chip
|= ((addr
>> (alen
* 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW
);
697 rc
= i2c_send(&state
, chip
, 0, I2CF_START_COND
, alen
, &xaddr
[4-alen
]);
699 if (gd
->have_console
)
700 printf("i2c_write: first i2c_send failed (%d)\n", rc
);
704 rc
= i2c_send(&state
, 0, 0, I2CF_STOP_COND
, len
, buffer
);
706 if (gd
->have_console
)
707 printf("i2c_write: second i2c_send failed (%d)\n", rc
);
711 rc
= i2c_doio(&state
);
713 if (gd
->have_console
)
714 printf("i2c_write: i2c_doio failed (%d)\n", rc
);
721 i2c_reg_read(uchar i2c_addr
, uchar reg
)
725 i2c_init(CFG_I2C_SPEED
, CFG_I2C_SLAVE
);
727 i2c_read(i2c_addr
, reg
, 1, &buf
, 1);
733 i2c_reg_write(uchar i2c_addr
, uchar reg
, uchar val
)
735 i2c_init(CFG_I2C_SPEED
, CFG_I2C_SLAVE
);
737 i2c_write(i2c_addr
, reg
, 1, &val
, 1);
740 #endif /* CONFIG_HARD_I2C */