2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
40 #include <asm/cache.h>
42 #if defined(CONFIG_OF_LIBFDT)
44 #include <libfdt_env.h>
45 #include <fdt_support.h>
48 DECLARE_GLOBAL_DATA_PTR
;
50 static char *cpu_warning
= "\n " \
51 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
53 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
54 !defined(CONFIG_MPC862))
56 static int check_CPU (long clock
, uint pvr
, uint immr
)
59 # if defined(CONFIG_MPC855)
61 # elif defined(CONFIG_MPC860P)
66 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
73 /* the highest 16 bits should be 0x0050 for a 860 */
75 if ((pvr
>> 16) != 0x0050)
78 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
83 * Some boards use sockets so different CPUs can be used.
84 * We have to check chip version in run time.
87 case 0x00020001: pre
= 'P'; break;
88 case 0x00030001: break;
89 case 0x00120003: suf
= "A"; break;
90 case 0x00130003: suf
= "A3"; break;
92 case 0x00200004: suf
= "B"; break;
94 case 0x00300004: suf
= "C"; break;
95 case 0x00310004: suf
= "C1"; m
= 1; break;
97 case 0x00200064: mid
= "SR"; suf
= "B"; break;
98 case 0x00300065: mid
= "SR"; suf
= "C"; break;
99 case 0x00310065: mid
= "SR"; suf
= "C1"; m
= 1; break;
100 case 0x05010000: suf
= "D3"; m
= 1; break;
101 case 0x05020000: suf
= "D4"; m
= 1; break;
102 /* this value is not documented anywhere */
103 case 0x40000000: pre
= 'P'; suf
= "D"; m
= 1; break;
104 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
105 case 0x08010004: /* Rev. A.0 */
108 case 0x08000003: /* Rev. 0.3 */
112 # if defined(CONFIG_MPC852T)
114 # elif defined(CONFIG_MPC859T)
116 # elif defined(CONFIG_MPC859DSL)
118 # elif defined(CONFIG_MPC866T)
121 "PC866x"; /* Unknown chip from MPC866 family */
124 case 0x09000000: pre
= 'M'; mid
= suf
= ""; m
= 1;
126 id_str
= "PC885"; /* 870/875/880/885 */
129 default: suf
= NULL
; break;
133 id_str
= "PC86x"; /* Unknown 86x chip */
135 printf ("%c%s%sZPnn%s", pre
, id_str
, mid
, suf
);
137 printf ("unknown M%s (0x%08x)", id_str
, k
);
140 #if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
141 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
143 CFG_8xx_CPUCLK_MIN
/ 1000000,
144 ((CFG_8xx_CPUCLK_MIN
% 1000000) + 50000) / 100000,
145 CFG_8xx_CPUCLK_MAX
/ 1000000,
146 ((CFG_8xx_CPUCLK_MAX
% 1000000) + 50000) / 100000
149 printf (" at %s MHz: ", strmhz (buf
, clock
));
151 printf ("%u kB I-Cache %u kB D-Cache",
152 checkicache () >> 10,
156 /* do we have a FEC (860T/P or 852/859/866/885)? */
158 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
159 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
160 printf (" FEC present");
170 if(clock
!= measure_gclk()) {
171 printf ("clock %ldHz != %dHz\n", clock
, measure_gclk());
178 #elif defined(CONFIG_MPC862)
180 static int check_CPU (long clock
, uint pvr
, uint immr
)
182 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
189 /* the highest 16 bits should be 0x0050 for a 8xx */
191 if ((pvr
>> 16) != 0x0050)
194 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
199 /* this value is not documented anywhere */
200 case 0x06000000: mid
= "P"; suf
= "0"; break;
201 case 0x06010001: mid
= "P"; suf
= "A"; m
= 1; break;
202 case 0x07000003: mid
= "P"; suf
= "B"; m
= 1; break;
203 default: suf
= NULL
; break;
206 #ifndef CONFIG_MPC857
208 printf ("%cPC862%sZPnn%s", pre
, mid
, suf
);
210 printf ("unknown MPC862 (0x%08x)", k
);
213 printf ("%cPC857TZPnn%s", pre
, suf
); /* only 857T tested right now! */
215 printf ("unknown MPC857 (0x%08x)", k
);
218 printf (" at %s MHz:", strmhz (buf
, clock
));
220 printf (" %u kB I-Cache", checkicache () >> 10);
221 printf (" %u kB D-Cache", checkdcache () >> 10);
223 /* lets check and see if we're running on a 862T (or P?) */
225 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
226 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
227 printf (" FEC present");
239 #elif defined(CONFIG_MPC823)
241 static int check_CPU (long clock
, uint pvr
, uint immr
)
243 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
248 /* the highest 16 bits should be 0x0050 for a 8xx */
250 if ((pvr
>> 16) != 0x0050)
253 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
258 case 0x20000000: suf
= "0"; break;
259 case 0x20010000: suf
= "0.1"; break;
260 case 0x20020000: suf
= "Z2/3"; break;
261 case 0x20020001: suf
= "Z3"; break;
262 case 0x21000000: suf
= "A"; break;
263 case 0x21010000: suf
= "B"; m
= 1; break;
264 case 0x21010001: suf
= "B2"; m
= 1; break;
266 case 0x24010000: suf
= NULL
;
267 puts ("PPC823EZTnnB2");
272 printf ("unknown MPC823 (0x%08x)", k
);
276 printf ("PPC823ZTnn%s", suf
);
278 printf (" at %s MHz:", strmhz (buf
, clock
));
280 printf (" %u kB I-Cache", checkicache () >> 10);
281 printf (" %u kB D-Cache", checkdcache () >> 10);
283 /* lets check and see if we're running on a 860T (or P?) */
285 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
286 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
287 puts (" FEC present");
299 #elif defined(CONFIG_MPC850)
301 static int check_CPU (long clock
, uint pvr
, uint immr
)
303 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
307 /* the highest 16 bits should be 0x0050 for a 8xx */
309 if ((pvr
>> 16) != 0x0050)
312 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
317 printf ("XPC850xxZT");
320 printf ("XPC850xxZTA");
323 printf ("XPC850xxZTB");
327 printf ("XPC850xxZTC");
331 printf ("unknown MPC850 (0x%08x)", k
);
333 printf (" at %s MHz:", strmhz (buf
, clock
));
335 printf (" %u kB I-Cache", checkicache () >> 10);
336 printf (" %u kB D-Cache", checkdcache () >> 10);
338 /* lets check and see if we're running on a 850T (or P?) */
340 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
341 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
342 printf (" FEC present");
356 /* ------------------------------------------------------------------------- */
360 ulong clock
= gd
->cpu_clk
;
361 uint immr
= get_immr (0); /* Return full IMMR contents */
362 uint pvr
= get_pvr ();
366 /* 850 has PARTNUM 20 */
367 /* 801 has PARTNUM 10 */
368 return check_CPU (clock
, pvr
, immr
);
371 /* ------------------------------------------------------------------------- */
373 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
374 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
376 int checkicache (void)
378 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
379 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
380 u32 cacheon
= rd_ic_cst () & IDC_ENABLED
;
383 u32 k
= memctl
->memc_br1
& ~0x00007fff; /* probe in flash memoryarea */
385 u32 k
= memctl
->memc_br0
& ~0x00007fff; /* probe in flash memoryarea */
390 wr_ic_cst (IDC_UNALL
);
391 wr_ic_cst (IDC_INVALL
);
392 wr_ic_cst (IDC_DISABLE
);
393 __asm__
volatile ("isync");
395 while (!((m
= rd_ic_cst ()) & IDC_CERR2
)) {
397 wr_ic_cst (IDC_LDLCK
);
398 __asm__
volatile ("isync");
401 k
+= 0x10; /* the number of bytes in a cacheline */
404 wr_ic_cst (IDC_UNALL
);
405 wr_ic_cst (IDC_INVALL
);
408 wr_ic_cst (IDC_ENABLE
);
410 wr_ic_cst (IDC_DISABLE
);
412 __asm__
volatile ("isync");
417 /* ------------------------------------------------------------------------- */
419 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
420 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
421 /* call with cache disabled */
423 int checkdcache (void)
425 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
426 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
427 u32 cacheon
= rd_dc_cst () & IDC_ENABLED
;
430 u32 k
= memctl
->memc_br1
& ~0x00007fff; /* probe in flash memoryarea */
432 u32 k
= memctl
->memc_br0
& ~0x00007fff; /* probe in flash memoryarea */
437 wr_dc_cst (IDC_UNALL
);
438 wr_dc_cst (IDC_INVALL
);
439 wr_dc_cst (IDC_DISABLE
);
441 while (!((m
= rd_dc_cst ()) & IDC_CERR2
)) {
443 wr_dc_cst (IDC_LDLCK
);
445 k
+= 0x10; /* the number of bytes in a cacheline */
448 wr_dc_cst (IDC_UNALL
);
449 wr_dc_cst (IDC_INVALL
);
452 wr_dc_cst (IDC_ENABLE
);
454 wr_dc_cst (IDC_DISABLE
);
459 /* ------------------------------------------------------------------------- */
461 void upmconfig (uint upm
, uint
* table
, uint size
)
465 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
466 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
468 for (i
= 0; i
< size
; i
++) {
469 memctl
->memc_mdr
= table
[i
]; /* (16-15) */
470 memctl
->memc_mcr
= addr
| upm
; /* (16-16) */
475 /* ------------------------------------------------------------------------- */
479 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
483 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
485 immap
->im_clkrst
.car_plprcr
|= PLPRCR_CSR
; /* Checkstop Reset enable */
487 /* Interrupts and MMU off */
488 __asm__
volatile ("mtspr 81, 0");
489 __asm__
volatile ("mfmsr %0":"=r" (msr
));
492 __asm__
volatile ("mtmsr %0"::"r" (msr
));
495 * Trying to execute the next instruction at a non-existing address
496 * should cause a machine check, resulting in reset
498 #ifdef CFG_RESET_ADDRESS
499 addr
= CFG_RESET_ADDRESS
;
502 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
503 * - sizeof (ulong) is usually a valid address. Better pick an address
504 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
505 * "(ulong)-1" used to be a good choice for many systems...
507 addr
= CFG_MONITOR_BASE
- sizeof (ulong
);
509 ((void (*)(void)) addr
) ();
513 #else /* CONFIG_LWMON */
516 * On the LWMON board, the MCLR reset input of the PIC's on the board
517 * uses a 47K/1n RC combination which has a 47us time constant. The
518 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
519 * and thus too short to reset the external hardware. So we use the
520 * watchdog to reset the board.
522 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
524 /* prevent triggering the watchdog */
525 disable_interrupts ();
527 /* make sure the watchdog is running */
528 reset_8xx_watchdog ((immap_t
*) CFG_IMMR
);
530 /* wait for watchdog reset */
537 #endif /* CONFIG_LWMON */
539 /* ------------------------------------------------------------------------- */
542 * Get timebase clock frequency (like cpu_clk in Hz)
544 * See sections 14.2 and 14.6 of the User's Manual
546 unsigned long get_tbclk (void)
548 uint immr
= get_immr (0); /* Return full IMMR contents */
549 volatile immap_t
*immap
= (volatile immap_t
*)(immr
& 0xFFFF0000);
550 ulong oscclk
, factor
, pll
;
552 if (immap
->im_clkrst
.car_sccr
& SCCR_TBS
) {
553 return (gd
->cpu_clk
/ 16);
556 pll
= immap
->im_clkrst
.car_plprcr
;
558 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
561 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
562 * factor is calculated as follows:
567 * factor = -----------------
570 * For older chips, it's just MF field of PLPRCR plus one.
572 if ((immr
& 0x0FFF) >= MPC8xx_NEW_CLK
) { /* MPC866/87x/88x series */
573 factor
= (PLPRCR_val(MFI
) + PLPRCR_val(MFN
)/(PLPRCR_val(MFD
)+1))/
574 (PLPRCR_val(PDF
)+1) / (1<<PLPRCR_val(S
));
576 factor
= PLPRCR_val(MF
)+1;
579 oscclk
= gd
->cpu_clk
/ factor
;
581 if ((immap
->im_clkrst
.car_sccr
& SCCR_RTSEL
) == 0 || factor
> 2) {
584 return (oscclk
/ 16);
587 /* ------------------------------------------------------------------------- */
589 #if defined(CONFIG_WATCHDOG)
590 void watchdog_reset (void)
592 int re_enable
= disable_interrupts ();
594 reset_8xx_watchdog ((immap_t
*) CFG_IMMR
);
596 enable_interrupts ();
598 #endif /* CONFIG_WATCHDOG */
600 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
602 void reset_8xx_watchdog (volatile immap_t
* immr
)
604 # if defined(CONFIG_LWMON)
606 * The LWMON board uses a MAX6301 Watchdog
607 * with the trigger pin connected to port PA.7
609 * (The old board version used a MAX706TESA Watchdog, which
610 * had to be handled exactly the same.)
612 # define WATCHDOG_BIT 0x0100
613 immr
->im_ioport
.iop_papar
&= ~(WATCHDOG_BIT
); /* GPIO */
614 immr
->im_ioport
.iop_padir
|= WATCHDOG_BIT
; /* Output */
615 immr
->im_ioport
.iop_paodr
&= ~(WATCHDOG_BIT
); /* active output */
617 immr
->im_ioport
.iop_padat
^= WATCHDOG_BIT
; /* Toggle WDI */
618 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
620 * The KUP4 boards uses a TPS3705 Watchdog
621 * with the trigger pin connected to port PA.5
623 # define WATCHDOG_BIT 0x0400
624 immr
->im_ioport
.iop_papar
&= ~(WATCHDOG_BIT
); /* GPIO */
625 immr
->im_ioport
.iop_padir
|= WATCHDOG_BIT
; /* Output */
626 immr
->im_ioport
.iop_paodr
&= ~(WATCHDOG_BIT
); /* active output */
628 immr
->im_ioport
.iop_padat
^= WATCHDOG_BIT
; /* Toggle WDI */
631 * All other boards use the MPC8xx Internal Watchdog
633 immr
->im_siu_conf
.sc_swsr
= 0x556c; /* write magic1 */
634 immr
->im_siu_conf
.sc_swsr
= 0xaa39; /* write magic2 */
635 # endif /* CONFIG_LWMON */
637 #endif /* CONFIG_WATCHDOG */