board/svm_sc8xx/svm_sc8xx.c

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8xx.h>
  26
  27 /* ------------------------------------------------------------------------- */
  28 const uint sdram_table[] =
  29 {
  30 /*-----------------
  31  UPM A contents:
  32 ----------------- */
  33 /*---------------------------------------------------
  34  Read Single Beat Cycle. Offset 0 in the RAM array.
  35 ---------------------------------------------------- */
  36 0x1f07fc04,  0xeeaefc04,  0x11adfc04,  0xefbbbc00 ,
  37 0x1ff77c47,  0x1ff77c35,  0xefeabc34,  0x1fb57c35 ,
  38 /*------------------------------------------------
  39  Read Burst Cycle. Offset 0x8 in the RAM array.
  40 ------------------------------------------------ */
  41 0x1f07fc04,  0xeeaefc04,  0x10adfc04,  0xf0affc00,
  42 0xf0affc00,  0xf1affc00,  0xefbbbc00,  0x1ff77c47,
  43 0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff,
  44 0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff,
  45 /*-------------------------------------------------------
  46  Write Single Beat Cycle. Offset 0x18 in the RAM array
  47 ------------------------------------------------------- */
  48 0x1f27fc04,  0xeeaebc00,  0x01b93c04,  0x1ff77c47 ,
  49 0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
  50 /*-------------------------------------------------
  51  Write Burst Cycle. Offset 0x20 in the RAM array
  52 ------------------------------------------------- */
  53 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  54 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff,
  55 0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
  56 0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
  57 /*------------------------------------------------------------------------
  58  Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
  59 ------------------------------------------------------------------------ */
  60 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  61 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
  62 0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
  63 /*-----------
  64 *  Exception:
  65 *  ----------- */
  66 0x7ffefc07,  0xffffffff,  0xffffffff,  0xffffffff ,
  67 };
  68
  69 /* ------------------------------------------------------------------------- */
  70 /*
  71  * Check Board Identity:
  72  *
  73  * Test ID string (SVM8...)
  74  *
  75  * Return 1 for "SC8xx" type, 0 else.
  76  */
  77
  78 int checkboard (void)
  79 {
  80     char *s = getenv("serial#");
  81     int board_type;
  82
  83     if (!s || strncmp(s, "SVM8", 4)) {
  84         printf ("### No HW ID - assuming SVM SC8xx\n");
  85         return (0);
  86     }
  87
  88     board_type = 1;
  89
  90     for (; *s; ++s) {
  91         if (*s == ' ')
  92             break;
  93         putc (*s);
  94     }
  95
  96     putc ('\n');
  97
  98     return (0);
  99 }
 100
 101 /* ------------------------------------------------------------------------- */
 102
 103 long int initdram (int board_type)
 104 {
 105         volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
 106         volatile memctl8xx_t *memctl = &immap->im_memctl;
 107         long int size_b0 = 0;
 108
 109         upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 110
 111         memctl->memc_mptpr = CFG_MPTPR;
 112 #if defined (CONFIG_SDRAM_16M)
 113         memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx;
 114         memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
 115         udelay(1);
 116         memctl->memc_mcr  = 0x80002830;
 117         udelay(1);
 118         memctl->memc_mar  = 0x00000088;
 119         udelay(1);
 120         memctl->memc_mcr  = 0x80002106;
 121         udelay(1);
 122         memctl->memc_or1 =  0xff000a00;
 123         size_b0 = 0x01000000;
 124 #elif defined (CONFIG_SDRAM_32M)
 125         memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx;
 126         memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
 127         udelay(1);
 128         memctl->memc_mcr  = 0x80002830;
 129         udelay(1);
 130         memctl->memc_mar  = 0x00000088;
 131         udelay(1);
 132         memctl->memc_mcr  = 0x80002106;
 133         udelay(1);
 134         memctl->memc_or1 =  0xfe000a00;
 135         size_b0 = 0x02000000;
 136 #elif defined (CONFIG_SDRAM_64M)
 137         memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx;
 138         memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
 139         udelay(1);
 140         memctl->memc_mcr  = 0x80002830;
 141         udelay(1);
 142         memctl->memc_mar  = 0x00000088;
 143         udelay(1);
 144         memctl->memc_mcr  = 0x80002106;
 145         udelay(1);
 146         memctl->memc_or1 =  0xfc000a00;
 147         size_b0 = 0x04000000;
 148 #else
 149 #error SDRAM size configuration missing.
 150 #endif
 151         memctl->memc_br1 =  0x00000081;
 152         udelay(200);
 153         return (size_b0 );
 154 }
 155
 156 #if defined(CONFIG_CMD_DOC)
 157 extern void doc_probe (ulong physadr);
 158 void doc_init (void)
 159 {
 160                 doc_probe (CFG_DOC_BASE);
 161 }
 162 #endif