1 /**************************************************************************
2 Etherboot - BOOTP/TFTP Bootstrap Program
3 Skeleton NIC driver for Etherboot
4 ***************************************************************************/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2, or (at
10 * your option) any later version.
14 * This file is a modified version from the Galileo polled mode
15 * network driver for the ethernet contained within the GT64260
16 * chip. It has been modified to fit into the U-Boot framework, from
17 * the original (etherboot) setup. Also, additional cleanup and features
20 * - Josh Huber <huber@mclx.com>
25 #include <galileo/gt64260R.h>
26 #include <galileo/core.h>
27 #include <asm/cache.h>
32 #include "eth_addrtbl.h"
34 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
36 #define GT6426x_ETH_BUF_SIZE 1536
38 /* if you like verbose output, turn this on! */
41 /* Restart autoneg if we detect link is up on phy init. */
44 * The GT doc's say that after Rst is deasserted, and the PHY
45 * reports autoneg complete, it runs through its autoneg
46 * procedures. This doesn't seem to be the case for MII
47 * PHY's. To work around this check for link up && autoneg
48 * complete when initilizing the port. If they are both set,
49 * then restart PHY autoneg. Of course, it may be something
50 * completly different.
52 #ifdef CONFIG_ETHER_PORT_MII
53 # define RESTART_AUTONEG
56 /* do this if you dont want to use snooping */
57 #define USE_SOFTWARE_CACHE_MANAGEMENT
59 #ifdef USE_SOFTWARE_CACHE_MANAGEMENT
60 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
61 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
62 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
64 /* bummer - w/o flush, nothing works, even with snooping - FIXME */
65 /* #define FLUSH_DCACHE(a,b) */
66 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
67 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
68 #define INVALIDATE_DCACHE(a,b)
71 eth0_tx_desc_single
*eth_tx_desc
;
72 eth0_rx_desc_single
*eth_rx_desc
;
74 char *eth_rx_buffer
[NR
];
77 unsigned int reg_base
;
81 #ifdef CONFIG_INTEL_LXT97X
82 /* for intel LXT972 */
83 static const char ether_port_phy_addr
[3]={0,1,2};
85 static const char ether_port_phy_addr
[3]={4,5,6};
88 /* MII PHY access routines are common for all i/f, use gal_ent0 */
89 #define GT6426x_MII_DEVNAME "gal_enet0"
91 int gt6426x_miiphy_read(char *devname
, unsigned char phy
,
92 unsigned char reg
, unsigned short *val
);
94 static inline unsigned short
95 miiphy_read_ret(unsigned short phy
, unsigned short reg
)
98 gt6426x_miiphy_read(GT6426x_MII_DEVNAME
,phy
,reg
,&val
);
103 /**************************************************************************
104 RESET - Reset adapter
105 ***************************************************************************/
107 gt6426x_eth_reset(void *v
)
109 /* we should do something here...
110 struct eth_device *wp = (struct eth_device *)v;
111 struct eth_dev_s *p = wp->priv;
115 /* put the card in its initial state */
118 static void gt6426x_handle_SMI(struct eth_dev_s
*p
, unsigned int icr
)
121 printf("SMI interrupt: ");
124 printf("SMI done\n");
130 psr
=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER
+ p
->reg_base
);
132 printf("PHY state change:\n"
135 psr
&8?" Link":"nLink",
139 #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
141 unsigned short mii_11
;
142 mii_11
=miiphy_read_ret(ether_port_phy_addr
[p
->dev
],0x11);
144 printf(" mii:%s:%s:%s:%s %s:%s %s\n",
145 mii_11
&(1<<14)?"100":" 10",
146 mii_11
&(1<<10)?" Link":"nLink",
147 mii_11
&(1<<9)?"FD":"HD",
148 mii_11
&(1<<4)?" FC":"nFC",
150 mii_11
&(1<<7)?"ANc":"ANnc",
151 mii_11
&(1<<8)?"AN":"Manual",
155 #endif /* CONFIG_INTEL_LXT97X */
161 gt6426x_eth_receive(struct eth_dev_s
*p
,unsigned int icr
)
166 eth0_rx_desc_single
*rx
=&p
->eth_rx_desc
[(p
->rdn
)];
168 INVALIDATE_DCACHE((unsigned int)rx
,(unsigned int)(rx
+1));
170 if (rx
->command_status
& 0x80000000) {
171 return 0; /* No packet received */
174 eth_len
= (unsigned int)
175 (rx
->buff_size_byte_count
) & 0x0000ffff;
176 eth_data
= (char *) p
->eth_rx_buffer
[p
->rdn
];
180 printf ("%s: Recived %d byte Packet @ 0x%p\n",
181 __FUNCTION__
, eth_len
, eth_data
);
186 * eth0_rx_buffer[RDN_ETH0];
189 /* let the upper layer handle the packet */
190 NetReceive ((uchar
*)eth_data
, eth_len
);
192 rx
->buff_size_byte_count
= GT6426x_ETH_BUF_SIZE
<<16;
196 rx
->command_status
= 0x80000000;
198 FLUSH_DCACHE((unsigned int)rx
,(unsigned int)(rx
+1));
201 if (p
->rdn
== NR
) {p
->rdn
= 0;}
206 GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER
+ p
->reg_base
, 0x00000080);
212 printf(" %02x", eth_data
[i
]);
215 printf(": %d bytes\n", eth_len
);
217 INVALIDATE_DCACHE((unsigned int)eth_data
,
218 (unsigned int)eth_data
+eth_len
);
222 /**************************************************************************
223 POLL - look for an rx frame, handle other conditions
224 ***************************************************************************/
226 gt6426x_eth_poll(void *v
)
228 struct eth_device
*wp
= (struct eth_device
*)v
;
229 struct eth_dev_s
*p
= wp
->priv
;
230 unsigned int icr
=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER
+ p
->reg_base
);
233 GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER
+p
->reg_base
, 0);
235 printf("poll got ICR %08x\n", icr
);
237 /* SMI done or PHY state change*/
238 if(icr
&0x30000000) gt6426x_handle_SMI(p
, icr
);
240 /* always process. We aren't using RX interrupts */
241 return gt6426x_eth_receive(p
, icr
);
244 /**************************************************************************
245 TRANSMIT - Transmit a frame
246 ***************************************************************************/
248 gt6426x_eth_transmit(void *v
, volatile char *p
, unsigned int s
)
250 struct eth_device
*wp
= (struct eth_device
*)v
;
251 struct eth_dev_s
*dev
= (struct eth_dev_s
*)wp
->priv
;
253 unsigned int old_command_stat
,old_psr
;
255 eth0_tx_desc_single
*tx
=&dev
->eth_tx_desc
[dev
->tdn
];
257 /* wait for tx to be ready */
258 INVALIDATE_DCACHE((unsigned int)tx
,(unsigned int)(tx
+1));
259 while (tx
->command_status
& 0x80000000) {
262 INVALIDATE_DCACHE((unsigned int)tx
,(unsigned int)(tx
+1));
265 GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0
+ dev
->reg_base
,
269 printf("copying to tx_buffer [%p], length %x, desc = %p\n",
270 dev
->eth_tx_buffer
, s
, dev
->eth_tx_desc
);
272 memcpy(dev
->eth_tx_buffer
, (char *) p
, s
);
274 tx
->buff_pointer
= (uchar
*)dev
->eth_tx_buffer
;
275 tx
->bytecount_reserved
= ((__u16
)s
) << 16;
279 * 18:16 - pad, last, first */
280 tx
->command_status
= (1<<31) | (1<<22) | (7<<16);
283 tx
->next_desc
= NULL
;
286 (struct eth0_tx_desc_struct
*)
287 &dev
->eth_tx_desc
[(dev
->tdn
+1)%NT
].bytecount_reserved
;
290 dev
->eth_tx_desc
[(dev
->tdn
+1)%NT
].command_status
= (7<<16); /* pad, last, first */
294 old_command_stat
=tx
->command_status
,
295 old_psr
=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER
+ dev
->reg_base
);
298 FLUSH_DCACHE((unsigned int)tx
,
299 (unsigned int)&dev
->eth_tx_desc
[(dev
->tdn
+2)%NT
]);
301 FLUSH_DCACHE((unsigned int)dev
->eth_tx_buffer
,(unsigned int)dev
->eth_tx_buffer
+s
);
303 GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER
+ dev
->reg_base
, 0x01000000);
307 unsigned int command_stat
=0;
308 printf("cmd_stat: %08x PSR: %08x\n", old_command_stat
, old_psr
);
309 /* wait for tx to be ready */
311 unsigned int psr
=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER
+ dev
->reg_base
);
312 command_stat
=tx
->command_status
;
313 if(command_stat
!=old_command_stat
|| psr
!=old_psr
) {
314 printf("cmd_stat: %08x PSR: %08x\n", command_stat
, psr
);
315 old_command_stat
= command_stat
;
318 /* gt6426x_eth0_poll(); */
319 } while (command_stat
& 0x80000000);
321 printf("sent %d byte frame\n", s
);
323 if((command_stat
& (3<<15)) == 3) {
324 printf("frame had error (stat=%08x)\n", command_stat
);
331 /**************************************************************************
332 DISABLE - Turn off ethernet interface
333 ***************************************************************************/
335 gt6426x_eth_disable(void *v
)
337 struct eth_device
*wp
= (struct eth_device
*)v
;
338 struct eth_dev_s
*p
= (struct eth_dev_s
*)wp
->priv
;
340 GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER
+ p
->reg_base
, 0x80008000);
343 /**************************************************************************
344 MII utilities - write: write to an MII register via SMI
345 ***************************************************************************/
347 gt6426x_miiphy_write(char *devname
, unsigned char phy
,
348 unsigned char reg
, unsigned short data
)
350 unsigned int temp
= (reg
<<21) | (phy
<<16) | data
;
352 while(GTREGREAD(ETHERNET_SMI_REGISTER
) & (1<<28)); /* wait for !Busy */
354 GT_REG_WRITE(ETHERNET_SMI_REGISTER
, temp
);
358 /**************************************************************************
359 MII utilities - read: read from an MII register via SMI
360 ***************************************************************************/
362 gt6426x_miiphy_read(char *devname
, unsigned char phy
,
363 unsigned char reg
, unsigned short *val
)
365 unsigned int temp
= (reg
<<21) | (phy
<<16) | 1<<26;
367 while(GTREGREAD(ETHERNET_SMI_REGISTER
) & (1<<28)); /* wait for !Busy */
369 GT_REG_WRITE(ETHERNET_SMI_REGISTER
, temp
);
372 temp
=GTREGREAD(ETHERNET_SMI_REGISTER
);
373 if(temp
& (1<<27)) break; /* wait for ReadValid */
375 *val
= temp
& 0xffff;
381 /**************************************************************************
382 MII utilities - dump mii registers
383 ***************************************************************************/
385 gt6426x_dump_mii(bd_t
*bis
, unsigned short phy
)
387 printf("mii reg 0 - 3: %04x %04x %04x %04x\n",
388 miiphy_read_ret(phy
, 0x0),
389 miiphy_read_ret(phy
, 0x1),
390 miiphy_read_ret(phy
, 0x2),
391 miiphy_read_ret(phy
, 0x3)
393 printf(" 4 - 7: %04x %04x %04x %04x\n",
394 miiphy_read_ret(phy
, 0x4),
395 miiphy_read_ret(phy
, 0x5),
396 miiphy_read_ret(phy
, 0x6),
397 miiphy_read_ret(phy
, 0x7)
400 miiphy_read_ret(phy
, 0x8)
402 printf(" 16-19: %04x %04x %04x %04x\n",
403 miiphy_read_ret(phy
, 0x10),
404 miiphy_read_ret(phy
, 0x11),
405 miiphy_read_ret(phy
, 0x12),
406 miiphy_read_ret(phy
, 0x13)
408 printf(" 20,30: %04x %04x\n",
409 miiphy_read_ret(phy
, 20),
410 miiphy_read_ret(phy
, 30)
415 #ifdef RESTART_AUTONEG
417 /* If link is up && autoneg compleate, and if
418 * GT and PHY disagree about link capabilitys,
419 * restart autoneg - something screwy with FD/HD
420 * unless we do this. */
422 check_phy_state(struct eth_dev_s
*p
)
424 int bmsr
= miiphy_read_ret(ether_port_phy_addr
[p
->dev
], PHY_BMSR
);
425 int psr
= GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER
+ p
->reg_base
);
427 if ((psr
& 1<<3) && (bmsr
& PHY_BMSR_LS
)) {
428 int nego
= miiphy_read_ret(ether_port_phy_addr
[p
->dev
], PHY_ANAR
) &
429 miiphy_read_ret(ether_port_phy_addr
[p
->dev
], PHY_ANLPAR
);
432 if (nego
& PHY_ANLPAR_TXFD
) {
434 printf("MII: 100Base-TX, Full Duplex\n");
435 } else if (nego
& PHY_ANLPAR_TX
) {
437 printf("MII: 100Base-TX, Half Duplex\n");
438 } else if (nego
& PHY_ANLPAR_10FD
) {
440 printf("MII: 10Base-T, Full Duplex\n");
441 } else if (nego
& PHY_ANLPAR_10
) {
443 printf("MII: 10Base-T, Half Duplex\n");
445 printf("MII: Unknown link-foo! %x\n", nego
);
449 if ((psr
& 0x3) != want
) {
450 printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
452 miiphy_write(GT6426x_MII_DEVNAME
,ether_port_phy_addr
[p
->dev
],0,
453 miiphy_read_ret(ether_port_phy_addr
[p
->dev
],0) | (1<<9));
454 udelay(10000); /* the EVB's GT takes a while to notice phy
461 /**************************************************************************
462 PROBE - Look for an adapter, this routine's visible to the outside
463 ***************************************************************************/
465 gt6426x_eth_probe(void *v
, bd_t
*bis
)
467 struct eth_device
*wp
= (struct eth_device
*)v
;
468 struct eth_dev_s
*p
= (struct eth_dev_s
*)wp
->priv
;
470 unsigned int reg_base
= p
->reg_base
;
474 if (( dev
< 0 ) || ( dev
>= GAL_ETH_DEVS
))
475 { /* This should never happen */
476 printf("%s: Invalid device %d\n", __FUNCTION__
, dev
);
481 printf ("%s: initializing %s\n", __FUNCTION__
, wp
->name
);
482 printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
483 GTREGREAD(COMM_UNIT_ARBITER_CONTROL
),
484 GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER
));
487 /* clear MIB counters */
489 temp
=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE
+ reg_base
+i
);
491 #ifdef CONFIG_INTEL_LXT97X
492 /* for intel LXT972 */
495 led 2: 0xc=link/rxact
496 led 3: 0x2=rxact (N/C)
497 strch: 0,2=30 ms, enable */
498 miiphy_write(GT6426x_MII_DEVNAME
,ether_port_phy_addr
[p
->dev
], 20, 0x1c22);
500 /* 2.7ns port rise time */
501 /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
503 /* already set up in mpsc.c */
504 /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */
506 /* already set up in sdram_init.S... */
507 /* MPSC0, MPSC1, RMII */
508 /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */
510 GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER
,
511 ether_port_phy_addr
[0] |
512 (ether_port_phy_addr
[1]<<5) |
513 (ether_port_phy_addr
[2]<<10)); /* 2000 */
515 /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes)
516 * 9 - 1: RIFB - interrupt on frame boundaries only
517 * 6:7 - 00: big endian rx and tx
518 * 5:2 - 1111: 15 retries */
519 GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER
+ reg_base
,
520 (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */
522 #ifndef USE_SOFTWARE_CACHE_MANAGEMENT
523 /* enable rx/tx desc/buffer cache snoop */
524 GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW
+ dev
*0x20,
526 temp
|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
527 GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW
+ dev
*0x20,
531 /* 31 28 27 24 23 20 19 16
532 * 0000 0000 0000 0000 [0004]
534 * 1000 1101 0000 0000 [4d00]
536 * 19 - 0=speed autoneg
537 * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
538 * 11 - no force link pass
539 * 10 - 1=disable fctl autoneg
540 * 8 - override prio ?? */
542 #ifndef CONFIG_ETHER_PORT_MII
543 temp
|= (1<<20); /* RMII */
546 GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER
+ reg_base
,
549 /* hardcode E1 also? */
550 /* -- according to dox, this is safer due to extra pulldowns? */
552 GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER
+ (dev
+1) * 0x400,
556 /* wake up MAC */ /* 2400 */
557 GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER
+ reg_base
, &temp
);
558 temp
|= (1<<7); /* enable port */
559 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
560 temp
|= (1<<12); /* hash size 1/2k */
562 temp
|= 1; /* promisc */
564 GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER
+ reg_base
, temp
);
567 #ifdef RESTART_AUTONEG
571 printf("%s: Waiting for link up..\n", wp
->name
);
573 /* wait for link back up */
574 while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER
+ reg_base
) & 8)
576 udelay(1000); /* wait 1 ms */
579 printf("%s: Failed!\n", wp
->name
);
583 printf("%s: OK!\n", wp
->name
);
587 p
->eth_tx_desc
[p
->tdn
].command_status
= 0;
589 /* Initialize Rx Side */
590 for (temp
= 0; temp
< NR
; temp
++) {
591 p
->eth_rx_desc
[temp
].buff_pointer
= (uchar
*)p
->eth_rx_buffer
[temp
];
592 p
->eth_rx_desc
[temp
].buff_size_byte_count
= GT6426x_ETH_BUF_SIZE
<<16;
595 p
->eth_rx_desc
[temp
].command_status
= 0x80000000;
596 p
->eth_rx_desc
[temp
].next_desc
=
597 (struct eth0_rx_desc_struct
*)
598 &p
->eth_rx_desc
[(temp
+1)%NR
].buff_size_byte_count
;
601 FLUSH_DCACHE((unsigned int)&p
->eth_tx_desc
[0],
602 (unsigned int)&p
->eth_tx_desc
[NR
]);
603 FLUSH_DCACHE((unsigned int)&p
->eth_rx_desc
[0],
604 (unsigned int)&p
->eth_rx_desc
[NR
]);
606 GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0
+ reg_base
,
607 (unsigned int) p
->eth_tx_desc
);
608 GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0
+ reg_base
,
609 (unsigned int) p
->eth_rx_desc
);
610 GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0
+ reg_base
,
611 (unsigned int) p
->eth_rx_desc
);
614 printf ("\nRx descriptor pointer is %08x %08x\n",
615 GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0
+ reg_base
),
616 GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0
+ reg_base
));
617 printf ("\n\n%08x %08x\n",
618 (unsigned int)p
->eth_rx_desc
,p
->eth_rx_desc
[0].command_status
);
620 printf ("Descriptor dump:\n");
621 printf ("cmd status: %08x\n",p
->eth_rx_desc
[0].command_status
);
622 printf ("byte_count: %08x\n",p
->eth_rx_desc
[0].buff_size_byte_count
);
623 printf ("buff_ptr: %08x\n",(unsigned int)p
->eth_rx_desc
[0].buff_pointer
);
624 printf ("next_desc: %08x\n\n",(unsigned int)p
->eth_rx_desc
[0].next_desc
);
625 printf ("%08x\n",*(unsigned int *) ((unsigned int)p
->eth_rx_desc
+ 0x0));
626 printf ("%08x\n",*(unsigned int *) ((unsigned int)p
->eth_rx_desc
+ 0x4));
627 printf ("%08x\n",*(unsigned int *) ((unsigned int)p
->eth_rx_desc
+ 0x8));
629 *(unsigned int *) ((unsigned int)p
->eth_rx_desc
+ 0xc));
633 gt6426x_dump_mii(bis
,ether_port_phy_addr
[p
->dev
]);
636 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
638 unsigned int hashtable_base
;
639 u8
*b
= (u8
*)(wp
->enetaddr
);
642 /* twist the MAC up into the way the discovery wants it */
643 macH
= (b
[0]<<8) | b
[1];
644 macL
= (b
[2]<<24) | (b
[3]<<16) | (b
[4]<<8) | b
[5];
646 /* mode 0, size 0x800 */
647 hashtable_base
=initAddressTable(dev
,0,1);
649 if(!hashtable_base
) {
650 printf("initAddressTable failed\n");
654 addAddressTableEntry(dev
, macH
, macL
, 1, 0);
655 GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER
+ reg_base
,
661 GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER
+ reg_base
, 0x00000080);
662 printf("%s: gt6426x eth device %d init success \n", wp
->name
, dev
);
666 /* enter all the galileo ethernet devs into MULTI-BOOT */
668 gt6426x_eth_initialize(bd_t
*bis
)
670 struct eth_device
*dev
;
673 char *s
, *e
, buf
[64];
676 printf( "\n%s\n", __FUNCTION
);
679 for (devnum
= 0; devnum
< GAL_ETH_DEVS
; devnum
++) {
680 dev
= calloc(sizeof(*dev
), 1);
682 printf( "%s: gal_enet%d allocation failure, %s\n",
683 __FUNCTION__
, devnum
, "eth_device structure");
687 /* must be less than NAMESIZE (16) */
688 sprintf(dev
->name
, "gal_enet%d", devnum
);
691 printf( "Initializing %s\n", dev
->name
);
694 /* Extract the MAC address from the environment */
697 case 0: s
= "ethaddr"; break;
698 #if (GAL_ETH_DEVS > 1)
699 case 1: s
= "eth1addr"; break;
701 #if (GAL_ETH_DEVS > 2)
702 case 2: s
= "eth2addr"; break;
704 default: /* this should never happen */
705 printf( "%s: Invalid device number %d\n",
706 __FUNCTION__
, devnum
);
710 temp
= getenv_r (s
, buf
, sizeof(buf
));
711 s
= (temp
> 0) ? buf
: NULL
;
714 printf ("Setting MAC %d to %s\n", devnum
, s
);
716 for (x
= 0; x
< 6; ++x
) {
717 dev
->enetaddr
[x
] = s
? simple_strtoul(s
, &e
, 16) : 0;
722 dev
->init
= (void*)gt6426x_eth_probe
;
723 dev
->halt
= (void*)gt6426x_eth_reset
;
724 dev
->send
= (void*)gt6426x_eth_transmit
;
725 dev
->recv
= (void*)gt6426x_eth_poll
;
727 p
= calloc( sizeof(*p
), 1 );
728 dev
->priv
= (void*)p
;
731 printf( "%s: %s allocation failure, %s\n",
732 __FUNCTION__
, dev
->name
, "Private Device Structure");
740 p
->reg_base
= devnum
* ETHERNET_PORTS_DIFFERENCE_OFFSETS
;
743 (eth0_tx_desc_single
*)
744 (((unsigned int) malloc(sizeof (eth0_tx_desc_single
) *
745 (NT
+1)) & 0xfffffff0) + 0x10);
748 printf( "%s: %s allocation failure, %s\n",
749 __FUNCTION__
, dev
->name
, "Tx Descriptor");
755 (eth0_rx_desc_single
*)
756 (((unsigned int) malloc(sizeof (eth0_rx_desc_single
) *
757 (NR
+1)) & 0xfffffff0) + 0x10);
760 printf( "%s: %s allocation failure, %s\n",
761 __FUNCTION__
, dev
->name
, "Rx Descriptor");
768 (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE
) & 0xfffffff0) + 0x10);
769 if (!p
->eth_tx_buffer
)
771 printf( "%s: %s allocation failure, %s\n",
772 __FUNCTION__
, dev
->name
, "Tx Bufffer");
775 free(p
->eth_rx_desc
);
779 for (temp
= 0 ; temp
< NR
; temp
++) {
780 p
->eth_rx_buffer
[temp
] =
782 (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE
) & 0xfffffff0) + 0x10);
783 if (!p
->eth_rx_buffer
[temp
])
785 printf( "%s: %s allocation failure, %s\n",
786 __FUNCTION__
, dev
->name
, "Rx Buffers");
789 free(p
->eth_tx_buffer
);
790 free(p
->eth_rx_desc
);
791 free(p
->eth_tx_desc
);
793 free(p
->eth_rx_buffer
[--temp
]);
800 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
801 miiphy_register(dev
->name
,
802 gt6426x_miiphy_read
, gt6426x_miiphy_write
);