board/esd/ash405/ash405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 #if 0
  33 #define FPGA_DEBUG
  34 #endif
  35
  36 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  37 extern void lxt971_no_sleep(void);
  38
  39 /* fpga configuration data - gzip compressed and generated by bin2c */
  40 const unsigned char fpgadata[] =
  41 {
  42 #include "fpgadata.c"
  43 };
  44
  45 /*
  46  * include common fpga code (for esd boards)
  47  */
  48 #include "../common/fpga.c"
  49
  50
  51 /* Prototypes */
  52 int gunzip(void *, int, unsigned char *, unsigned long *);
  53
  54
  55 int board_early_init_f (void)
  56 {
  57         /*
  58          * IRQ 0-15  405GP internally generated; active high; level sensitive
  59          * IRQ 16    405GP internally generated; active low; level sensitive
  60          * IRQ 17-24 RESERVED
  61          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  62          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  63          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  64          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  65          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  66          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  67          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  68          */
  69         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  70         mtdcr(uicer, 0x00000000);       /* disable all ints */
  71         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  72         mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
  73         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  74         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  75         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  76
  77         /*
  78          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  79          */
  80         mtebc (epcr, 0xa8400000); /* ebc always driven */
  81
  82         return 0;
  83 }
  84
  85
  86 /* ------------------------------------------------------------------------- */
  87
  88 int misc_init_f (void)
  89 {
  90         return 0;  /* dummy implementation */
  91 }
  92
  93
  94 int misc_init_r (void)
  95 {
  96         volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
  97         volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
  98         volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
  99         volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
 100         unsigned char *dst;
 101         ulong len = sizeof(fpgadata);
 102         int status;
 103         int index;
 104         int i;
 105
 106         dst = malloc(CFG_FPGA_MAX_SIZE);
 107         if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 108                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 109                 do_reset (NULL, 0, 0, NULL);
 110         }
 111
 112         status = fpga_boot(dst, len);
 113         if (status != 0) {
 114                 printf("\nFPGA: Booting failed ");
 115                 switch (status) {
 116                 case ERROR_FPGA_PRG_INIT_LOW:
 117                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 118                         break;
 119                 case ERROR_FPGA_PRG_INIT_HIGH:
 120                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 121                         break;
 122                 case ERROR_FPGA_PRG_DONE:
 123                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 124                         break;
 125                 }
 126
 127                 /* display infos on fpgaimage */
 128                 index = 15;
 129                 for (i=0; i<4; i++) {
 130                         len = dst[index];
 131                         printf("FPGA: %s\n", &(dst[index+1]));
 132                         index += len+3;
 133                 }
 134                 putc ('\n');
 135                 /* delayed reboot */
 136                 for (i=20; i>0; i--) {
 137                         printf("Rebooting in %2d seconds \r",i);
 138                         for (index=0;index<1000;index++)
 139                                 udelay(1000);
 140                 }
 141                 putc ('\n');
 142                 do_reset(NULL, 0, 0, NULL);
 143         }
 144
 145         puts("FPGA:  ");
 146
 147         /* display infos on fpgaimage */
 148         index = 15;
 149         for (i=0; i<4; i++) {
 150                 len = dst[index];
 151                 printf("%s ", &(dst[index+1]));
 152                 index += len+3;
 153         }
 154         putc ('\n');
 155
 156         free(dst);
 157
 158         /*
 159          * Reset FPGA via FPGA_DATA pin
 160          */
 161         SET_FPGA(FPGA_PRG | FPGA_CLK);
 162         udelay(1000); /* wait 1ms */
 163         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 164         udelay(1000); /* wait 1ms */
 165
 166         /*
 167          * Reset external DUARTs
 168          */
 169         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
 170         udelay(10); /* wait 10us */
 171         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
 172         udelay(1000); /* wait 1ms */
 173
 174         /*
 175          * Enable interrupts in exar duart mcr[3]
 176          */
 177         *duart0_mcr = 0x08;
 178         *duart1_mcr = 0x08;
 179         *duart2_mcr = 0x08;
 180         *duart3_mcr = 0x08;
 181
 182         return (0);
 183 }
 184
 185
 186 /*
 187  * Check Board Identity:
 188  */
 189
 190 int checkboard (void)
 191 {
 192         char str[64];
 193         int i = getenv_r ("serial#", str, sizeof(str));
 194
 195         puts ("Board: ");
 196
 197         if (i == -1) {
 198                 puts ("### No HW ID - assuming ASH405");
 199         } else {
 200                 puts(str);
 201         }
 202
 203         putc ('\n');
 204
 205         return 0;
 206 }
 207
 208 /* ------------------------------------------------------------------------- */
 209
 210 long int initdram (int board_type)
 211 {
 212         unsigned long val;
 213
 214         mtdcr(memcfga, mem_mb0cf);
 215         val = mfdcr(memcfgd);
 216
 217         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 218 }
 219
 220 /* ------------------------------------------------------------------------- */
 221
 222 void reset_phy(void)
 223 {
 224 #ifdef CONFIG_LXT971_NO_SLEEP
 225         /*
 226          * Disable sleep mode in LXT971
 227          */
 228         lxt971_no_sleep();
 229 #endif
 230 }