cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_QE
  30 extern qe_iop_conf_t qe_iop_conf_tab[];
  31 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  32                          int open_drain, int assign);
  33 extern void qe_init(uint qe_base);
  34 extern void qe_reset(void);
  35
  36 static void config_qe_ioports(void)
  37 {
  38         u8      port, pin;
  39         int     dir, open_drain, assign;
  40         int     i;
  41
  42         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  43                 port            = qe_iop_conf_tab[i].port;
  44                 pin             = qe_iop_conf_tab[i].pin;
  45                 dir             = qe_iop_conf_tab[i].dir;
  46                 open_drain      = qe_iop_conf_tab[i].open_drain;
  47                 assign          = qe_iop_conf_tab[i].assign;
  48                 qe_config_iopin(port, pin, dir, open_drain, assign);
  49         }
  50 }
  51 #endif
  52
  53 /*
  54  * Breathe some life into the CPU...
  55  *
  56  * Set up the memory map,
  57  * initialize a bunch of registers,
  58  * initialize the UPM's
  59  */
  60 void cpu_init_f (volatile immap_t * im)
  61 {
  62         /* Pointer is writable since we allocated a register for it */
  63         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
  64
  65         /* Clear initial global data */
  66         memset ((void *) gd, 0, sizeof (gd_t));
  67
  68         /* system performance tweaking */
  69
  70 #ifdef CFG_ACR_PIPE_DEP
  71         /* Arbiter pipeline depth */
  72         im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  73                           (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  74 #endif
  75
  76 #ifdef CFG_ACR_RPTCNT
  77         /* Arbiter repeat count */
  78         im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  79                           (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
  80 #endif
  81
  82 #ifdef CFG_SPCR_OPT
  83         /* Optimize transactions between CSB and other devices */
  84         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  85                            (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
  86 #endif
  87
  88 #ifdef CFG_SPCR_TSECEP
  89         /* all eTSEC's Emergency priority */
  90         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
  91                            (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
  92 #endif
  93
  94 #ifdef CFG_SPCR_TSEC1EP
  95         /* TSEC1 Emergency priority */
  96         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
  97                            (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
  98 #endif
  99
 100 #ifdef CFG_SPCR_TSEC2EP
 101         /* TSEC2 Emergency priority */
 102         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
 103                            (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
 104 #endif
 105
 106 #ifdef CFG_SCCR_ENCCM
 107         /* Encryption clock mode */
 108         im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
 109                        (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
 110 #endif
 111
 112 #ifdef CFG_SCCR_PCICM
 113         /* PCI & DMA clock mode */
 114         im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
 115                        (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
 116 #endif
 117
 118 #ifdef CFG_SCCR_TSECCM
 119         /* all TSEC's clock mode */
 120         im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
 121                        (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
 122 #endif
 123
 124 #ifdef CFG_SCCR_TSEC1CM
 125         /* TSEC1 clock mode */
 126         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
 127                        (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
 128 #endif
 129
 130 #ifdef CFG_SCCR_TSEC2CM
 131         /* TSEC2 clock mode */
 132         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
 133                        (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
 134 #endif
 135
 136 #ifdef CFG_SCCR_TSEC1ON
 137         /* TSEC1 clock switch */
 138         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
 139                        (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
 140 #endif
 141
 142 #ifdef CFG_SCCR_TSEC2ON
 143         /* TSEC2 clock switch */
 144         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
 145                        (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
 146 #endif
 147
 148 #ifdef CFG_SCCR_USBMPHCM
 149         /* USB MPH clock mode */
 150         im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
 151                        (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
 152 #endif
 153
 154 #ifdef CFG_SCCR_USBDRCM
 155         /* USB DR clock mode */
 156         im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
 157                        (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
 158 #endif
 159
 160 #ifdef CFG_SCCR_SATACM
 161         /* SATA controller clock mode */
 162         im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
 163                        (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
 164 #endif
 165
 166         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 167         gd->reset_status = im->reset.rsr;
 168         im->reset.rsr = ~(RSR_RES);
 169
 170         /*
 171          * RMR - Reset Mode Register
 172          * contains checkstop reset enable (4.6.1.4)
 173          */
 174         im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
 175
 176         /* LCRR - Clock Ratio Register (10.3.1.16) */
 177         im->lbus.lcrr = CFG_LCRR;
 178
 179         /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
 180         im->sysconf.spcr |= SPCR_TBEN;
 181
 182         /* System General Purpose Register */
 183 #ifdef CFG_SICRH
 184         im->sysconf.sicrh = CFG_SICRH;
 185 #endif
 186 #ifdef CFG_SICRL
 187         im->sysconf.sicrl = CFG_SICRL;
 188 #endif
 189         /* DDR control driver register */
 190 #ifdef CFG_DDRCDR
 191         im->sysconf.ddrcdr = CFG_DDRCDR;
 192 #endif
 193         /* Output buffer impedance register */
 194 #ifdef CFG_OBIR
 195         im->sysconf.obir = CFG_OBIR;
 196 #endif
 197
 198 #ifdef CONFIG_QE
 199         /* Config QE ioports */
 200         config_qe_ioports();
 201 #endif
 202
 203         /*
 204          * Memory Controller:
 205          */
 206
 207         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 208          * addresses - these have to be modified later when FLASH size
 209          * has been determined
 210          */
 211
 212 #if defined(CFG_BR0_PRELIM)  \
 213         && defined(CFG_OR0_PRELIM) \
 214         && defined(CFG_LBLAWBAR0_PRELIM) \
 215         && defined(CFG_LBLAWAR0_PRELIM)
 216         im->lbus.bank[0].br = CFG_BR0_PRELIM;
 217         im->lbus.bank[0].or = CFG_OR0_PRELIM;
 218         im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
 219         im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
 220 #else
 221 #error  CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
 222 #endif
 223
 224 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
 225         im->lbus.bank[1].br = CFG_BR1_PRELIM;
 226         im->lbus.bank[1].or = CFG_OR1_PRELIM;
 227 #endif
 228 #if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
 229         im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
 230         im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
 231 #endif
 232 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 233         im->lbus.bank[2].br = CFG_BR2_PRELIM;
 234         im->lbus.bank[2].or = CFG_OR2_PRELIM;
 235 #endif
 236 #if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
 237         im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
 238         im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
 239 #endif
 240 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 241         im->lbus.bank[3].br = CFG_BR3_PRELIM;
 242         im->lbus.bank[3].or = CFG_OR3_PRELIM;
 243 #endif
 244 #if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
 245         im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
 246         im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
 247 #endif
 248 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
 249         im->lbus.bank[4].br = CFG_BR4_PRELIM;
 250         im->lbus.bank[4].or = CFG_OR4_PRELIM;
 251 #endif
 252 #if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
 253         im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
 254         im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
 255 #endif
 256 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
 257         im->lbus.bank[5].br = CFG_BR5_PRELIM;
 258         im->lbus.bank[5].or = CFG_OR5_PRELIM;
 259 #endif
 260 #if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
 261         im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
 262         im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
 263 #endif
 264 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 265         im->lbus.bank[6].br = CFG_BR6_PRELIM;
 266         im->lbus.bank[6].or = CFG_OR6_PRELIM;
 267 #endif
 268 #if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
 269         im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
 270         im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
 271 #endif
 272 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 273         im->lbus.bank[7].br = CFG_BR7_PRELIM;
 274         im->lbus.bank[7].or = CFG_OR7_PRELIM;
 275 #endif
 276 #if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
 277         im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
 278         im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
 279 #endif
 280 #ifdef CFG_GPIO1_PRELIM
 281         im->gpio[0].dir = CFG_GPIO1_DIR;
 282         im->gpio[0].dat = CFG_GPIO1_DAT;
 283 #endif
 284 #ifdef CFG_GPIO2_PRELIM
 285         im->gpio[1].dir = CFG_GPIO2_DIR;
 286         im->gpio[1].dat = CFG_GPIO2_DAT;
 287 #endif
 288 }
 289
 290 int cpu_init_r (void)
 291 {
 292 #ifdef CONFIG_QE
 293         uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
 294         qe_init(qe_base);
 295         qe_reset();
 296 #endif
 297         return 0;
 298 }
 299
 300 /*
 301  * Figure out the cause of the reset
 302  */
 303 int prt_83xx_rsr(void)
 304 {
 305         static struct {
 306                 ulong mask;
 307                 char *desc;
 308         } bits[] = {
 309                 {
 310                 RSR_SWSR, "Software Soft"}, {
 311                 RSR_SWHR, "Software Hard"}, {
 312                 RSR_JSRS, "JTAG Soft"}, {
 313                 RSR_CSHR, "Check Stop"}, {
 314                 RSR_SWRS, "Software Watchdog"}, {
 315                 RSR_BMRS, "Bus Monitor"}, {
 316                 RSR_SRS,  "External/Internal Soft"}, {
 317                 RSR_HRS,  "External/Internal Hard"}
 318         };
 319         static int n = sizeof bits / sizeof bits[0];
 320         ulong rsr = gd->reset_status;
 321         int i;
 322         char *sep;
 323
 324         puts("Reset Status:");
 325
 326         sep = " ";
 327         for (i = 0; i < n; i++)
 328                 if (rsr & bits[i].mask) {
 329                         printf("%s%s", sep, bits[i].desc);
 330                         sep = ", ";
 331                 }
 332         puts("\n\n");
 333         return 0;
 334 }