2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
31 * Wolfgang Denk <wd@denx.de>
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
37 * Marius Groeger <mag@sysgo.de>
39 * added HiP7 (824x/827x/8280) processors support by
40 * Yuli Barcohen <yuli@arabellasw.com>
47 #include <asm/processor.h>
48 #include <asm/cpm_8260.h>
50 #if defined(CONFIG_OF_LIBFDT)
52 #include <libfdt_env.h>
53 #include <fdt_support.h>
56 DECLARE_GLOBAL_DATA_PTR
;
58 #if defined(CONFIG_GET_CPU_STR_F)
59 extern int get_cpu_str_f (char *buf
);
64 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
65 ulong clock
= gd
->cpu_clk
;
66 uint pvr
= get_pvr ();
86 return -1; /* whoops! not an MPC8260 */
90 immr
= immap
->im_memctl
.memc_immr
;
91 if ((immr
& IMMR_ISB_MSK
) != CFG_IMMR
)
92 return -1; /* whoops! someone moved the IMMR */
94 #if defined(CONFIG_GET_CPU_STR_F)
96 printf ("%s (HiP%d Rev %02x, Mask ", buf
, k
, rev
);
98 printf (CPU_ID_STR
" (HiP%d Rev %02x, Mask ", k
, rev
);
102 * the bottom 16 bits of the immr are the Part Number and Mask Number
103 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
104 * RISC Microcode Revision Number (13-10).
105 * For the 8260, Motorola doesn't include the Microcode Revision
108 m
= immr
& (IMMR_PARTNUM_MSK
| IMMR_MASKNUM_MSK
);
109 k
= *((ushort
*) & immap
->im_dprambase
[PROFF_REVNUM
]);
119 puts ("A.1 1K22A-XC");
125 puts ("B.2 2K23A-XC");
134 puts ("A.0(A) 2K25A");
164 printf ("unknown [immr=0x%04x,k=0x%04x]", m
, k
);
168 printf (") at %s MHz\n", strmhz (buf
, clock
));
173 /* ------------------------------------------------------------------------- */
174 /* configures a UPM by writing into the UPM RAM array */
175 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
176 /* NOTE: the physical address chosen must not overlap into any other area */
177 /* mapped by the memory controller because bank 11 has the lowest priority */
179 void upmconfig (uint upm
, uint
* table
, uint size
)
181 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
182 volatile memctl8260_t
*memctl
= &immap
->im_memctl
;
183 volatile uchar
*dummy
= (uchar
*) BRx_BA_MSK
; /* set all BA bits */
186 /* first set up bank 11 to reference the correct UPM at a dummy address */
188 memctl
->memc_or11
= ORxU_AM_MSK
; /* set all AM bits */
194 ((uint
)dummy
& BRx_BA_MSK
) | BRx_PS_32
| BRx_MS_UPMA
|
196 memctl
->memc_mamr
= MxMR_OP_WARR
;
201 ((uint
)dummy
& BRx_BA_MSK
) | BRx_PS_32
| BRx_MS_UPMB
|
203 memctl
->memc_mbmr
= MxMR_OP_WARR
;
208 ((uint
)dummy
& BRx_BA_MSK
) | BRx_PS_32
| BRx_MS_UPMC
|
210 memctl
->memc_mcmr
= MxMR_OP_WARR
;
214 panic ("upmconfig passed invalid UPM number (%u)\n", upm
);
220 * at this point, the dummy address is set up to access the selected UPM,
221 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
223 * now we simply load the mdr with each word and poke the dummy address.
224 * the MAD is incremented on each access.
227 for (i
= 0; i
< size
; i
++) {
228 memctl
->memc_mdr
= table
[i
];
232 /* now kill bank 11 */
233 memctl
->memc_br11
= 0;
236 /* ------------------------------------------------------------------------- */
238 #if !defined(CONFIG_HAVE_OWN_RESET)
240 do_reset (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
244 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
246 immap
->im_clkrst
.car_rmr
= RMR_CSRE
; /* Checkstop Reset enable */
248 /* Interrupts and MMU off */
249 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
251 msr
&= ~(MSR_ME
| MSR_EE
| MSR_IR
| MSR_DR
);
252 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
255 * Trying to execute the next instruction at a non-existing address
256 * should cause a machine check, resulting in reset
258 #ifdef CFG_RESET_ADDRESS
259 addr
= CFG_RESET_ADDRESS
;
262 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
263 * - sizeof (ulong) is usually a valid address. Better pick an address
264 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
266 addr
= CFG_MONITOR_BASE
- sizeof (ulong
);
268 ((void (*)(void)) addr
) ();
272 #endif /* CONFIG_HAVE_OWN_RESET */
274 /* ------------------------------------------------------------------------- */
277 * Get timebase clock frequency (like cpu_clk in Hz)
280 unsigned long get_tbclk (void)
284 tbclk
= (gd
->bus_clk
+ 3L) / 4L;
289 /* ------------------------------------------------------------------------- */
291 #if defined(CONFIG_WATCHDOG)
292 void watchdog_reset (void)
294 int re_enable
= disable_interrupts ();
296 reset_8260_watchdog ((immap_t
*) CFG_IMMR
);
298 enable_interrupts ();
300 #endif /* CONFIG_WATCHDOG */
302 /* ------------------------------------------------------------------------- */
303 #if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
304 void ft_cpu_setup (void *blob
, bd_t
*bd
)
306 char * cpu_path
= "/cpus/" OF_CPU
;
308 do_fixup_by_path_u32(blob
, cpu_path
, "bus-frequency", bd
->bi_busfreq
, 1);
309 do_fixup_by_path_u32(blob
, cpu_path
, "timebase-frequency", OF_TBCLK
, 1);
310 do_fixup_by_path_u32(blob
, cpu_path
, "clock-frequency", bd
->bi_intfreq
, 1);
312 #endif /* CONFIG_OF_LIBFDT */