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config-gta02v5-beyond.patch
[u-boot-openmoko/mini2440.git] / drivers / usb / usb_ohci.c
blobf60d4310cb2a68af76e42352385222d2795a59f3
1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
3 *
4 * Interrupt support is added. Now, it has been tested
5 * on ULI1575 chip and works well with USB keyboard.
6 *
7 * (C) Copyright 2007
8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
9 *
10 * (C) Copyright 2003
11 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
12 *
13 * Note: Much of this code has been derived from Linux 2.4
14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
15 * (C) Copyright 2000-2002 David Brownell
16 *
17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
18 * ebenard@eukrea.com - based on s3c24x0's driver
19 *
20 * See file CREDITS for list of people who contributed to this
21 * project.
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * MA 02111-1307 USA
37 *
38 */
39 /*
40 * IMPORTANT NOTES
41 * 1 - Read doc/README.generic_usb_ohci
42 * 2 - this driver is intended for use with USB Mass Storage Devices
43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
45 * to activate workaround for bug #41 or this driver will NOT work!
46 */
47
48 #include <common.h>
49
50 #ifdef CONFIG_USB_OHCI_NEW
51
52 #include <asm/byteorder.h>
53
54 #if defined(CONFIG_PCI_OHCI)
55 # include <pci.h>
56 #endif
57
58 #include <malloc.h>
59 #include <usb.h>
60 #include "usb_ohci.h"
61
62 #ifdef CONFIG_AT91RM9200
63 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
64 #endif
65
66 #if defined(CONFIG_ARM920T) || \
67 defined(CONFIG_S3C2400) || \
68 defined(CONFIG_S3C2410) || \
69 defined(CONFIG_S3C2440) || \
70 defined(CONFIG_S3C2443) || \
71 defined(CONFIG_440EP) || \
72 defined(CONFIG_PCI_OHCI) || \
73 defined(CONFIG_MPC5200) || \
74 defined(CFG_OHCI_USE_NPS)
75 # define OHCI_USE_NPS /* force NoPowerSwitching mode */
76 #endif
77
78 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
79 #undef DEBUG
80 #undef SHOW_INFO
81 #undef OHCI_FILL_TRACE
82
83 /* For initializing controller (mask in an HCFS mode too) */
84 #define OHCI_CONTROL_INIT \
85 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
86
87 /*
88 * e.g. PCI controllers need this
89 */
90 #ifdef CFG_OHCI_SWAP_REG_ACCESS
91 # define readl(a) __swap_32(*((vu_long *)(a)))
92 # define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
93 #else
94 # define readl(a) (*((vu_long *)(a)))
95 # define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
96 #endif /* CFG_OHCI_SWAP_REG_ACCESS */
97
98 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
99
100 #ifdef CONFIG_PCI_OHCI
101 static struct pci_device_id ohci_pci_ids[] = {
102 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
103 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
104 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
105 /* Please add supported PCI OHCI controller ids here */
106 {0, 0}
107 };
108 #endif
109
110 #ifdef DEBUG
111 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
112 #else
113 #define dbg(format, arg...) do {} while(0)
114 #endif /* DEBUG */
115 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
116 #undef SHOW_INFO
117 #ifdef SHOW_INFO
118 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
119 #else
120 #define info(format, arg...) do {} while(0)
121 #endif
122
123 #ifdef CFG_OHCI_BE_CONTROLLER
124 # define m16_swap(x) cpu_to_be16(x)
125 # define m32_swap(x) cpu_to_be32(x)
126 #else
127 # define m16_swap(x) cpu_to_le16(x)
128 # define m32_swap(x) cpu_to_le32(x)
129 #endif /* CFG_OHCI_BE_CONTROLLER */
130
131 /* global ohci_t */
132 static ohci_t gohci;
133 /* this must be aligned to a 256 byte boundary */
134 struct ohci_hcca ghcca[1];
135 /* a pointer to the aligned storage */
136 struct ohci_hcca *phcca;
137 /* this allocates EDs for all possible endpoints */
138 struct ohci_device ohci_dev;
139 /* RHSC flag */
140 int got_rhsc;
141 /* device which was disconnected */
142 struct usb_device *devgone;
143
144 /*-------------------------------------------------------------------------*/
145
146 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
147 * The erratum (#4) description is incorrect. AMD's workaround waits
148 * till some bits (mostly reserved) are clear; ok for all revs.
149 */
150 #define OHCI_QUIRK_AMD756 0xabcd
151 #define read_roothub(hc, register, mask) ({ \
152 u32 temp = readl (&hc->regs->roothub.register); \
153 if (hc->flags & OHCI_QUIRK_AMD756) \
154 while (temp & mask) \
155 temp = readl (&hc->regs->roothub.register); \
156 temp; })
157
158 static u32 roothub_a (struct ohci *hc)
159 { return read_roothub (hc, a, 0xfc0fe000); }
160 static inline u32 roothub_b (struct ohci *hc)
161 { return readl (&hc->regs->roothub.b); }
162 static inline u32 roothub_status (struct ohci *hc)
163 { return readl (&hc->regs->roothub.status); }
164 static u32 roothub_portstatus (struct ohci *hc, int i)
165 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
166
167 /* forward declaration */
168 static int hc_interrupt (void);
169 static void
170 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
171 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
172
173 /*-------------------------------------------------------------------------*
174 * URB support functions
175 *-------------------------------------------------------------------------*/
176
177 /* free HCD-private data associated with this URB */
178
179 static void urb_free_priv (urb_priv_t * urb)
180 {
181 int i;
182 int last;
183 struct td * td;
184
185 last = urb->length - 1;
186 if (last >= 0) {
187 for (i = 0; i <= last; i++) {
188 td = urb->td[i];
189 if (td) {
190 td->usb_dev = NULL;
191 urb->td[i] = NULL;
192 }
193 }
194 }
195 free(urb);
196 }
197
198 /*-------------------------------------------------------------------------*/
199
200 #ifdef DEBUG
201 static int sohci_get_current_frame_number (struct usb_device * dev);
202
203 /* debug| print the main components of an URB
204 * small: 0) header + data packets 1) just header */
205
206 static void pkt_print (urb_priv_t *purb, struct usb_device * dev,
207 unsigned long pipe, void * buffer,
208 int transfer_len, struct devrequest * setup, char * str, int small)
209 {
210 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
211 str,
212 sohci_get_current_frame_number (dev),
213 usb_pipedevice (pipe),
214 usb_pipeendpoint (pipe),
215 usb_pipeout (pipe)? 'O': 'I',
216 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
217 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
218 (purb ? purb->actual_length : 0),
219 transfer_len, dev->status);
220 #ifdef OHCI_VERBOSE_DEBUG
221 if (!small) {
222 int i, len;
223
224 if (usb_pipecontrol (pipe)) {
225 printf (__FILE__ ": cmd(8):");
226 for (i = 0; i < 8 ; i++)
227 printf (" %02x", ((__u8 *) setup) [i]);
228 printf ("\n");
229 }
230 if (transfer_len > 0 && buffer) {
231 printf (__FILE__ ": data(%d/%d):",
232 (purb ? purb->actual_length : 0),
233 transfer_len);
234 len = usb_pipeout (pipe)?
235 transfer_len:
236 (purb ? purb->actual_length : 0);
237 for (i = 0; i < 16 && i < len; i++)
238 printf (" %02x", ((__u8 *) buffer) [i]);
239 printf ("%s\n", i < len? "...": "");
240 }
241 }
242 #endif
243 }
244
245 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
246 void ep_print_int_eds (ohci_t *ohci, char * str) {
247 int i, j;
248 __u32 * ed_p;
249 for (i= 0; i < 32; i++) {
250 j = 5;
251 ed_p = &(ohci->hcca->int_table [i]);
252 if (*ed_p == 0)
253 continue;
254 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
255 while (*ed_p != 0 && j--) {
256 ed_t *ed = (ed_t *)m32_swap(ed_p);
257 printf (" ed: %4x;", ed->hwINFO);
258 ed_p = &ed->hwNextED;
259 }
260 printf ("\n");
261 }
262 }
263
264 static void ohci_dump_intr_mask (char *label, __u32 mask)
265 {
266 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
267 label,
268 mask,
269 (mask & OHCI_INTR_MIE) ? " MIE" : "",
270 (mask & OHCI_INTR_OC) ? " OC" : "",
271 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
272 (mask & OHCI_INTR_FNO) ? " FNO" : "",
273 (mask & OHCI_INTR_UE) ? " UE" : "",
274 (mask & OHCI_INTR_RD) ? " RD" : "",
275 (mask & OHCI_INTR_SF) ? " SF" : "",
276 (mask & OHCI_INTR_WDH) ? " WDH" : "",
277 (mask & OHCI_INTR_SO) ? " SO" : ""
278 );
279 }
280
281 static void maybe_print_eds (char *label, __u32 value)
282 {
283 ed_t *edp = (ed_t *)value;
284
285 if (value) {
286 dbg ("%s %08x", label, value);
287 dbg ("%08x", edp->hwINFO);
288 dbg ("%08x", edp->hwTailP);
289 dbg ("%08x", edp->hwHeadP);
290 dbg ("%08x", edp->hwNextED);
291 }
292 }
293
294 static char * hcfs2string (int state)
295 {
296 switch (state) {
297 case OHCI_USB_RESET: return "reset";
298 case OHCI_USB_RESUME: return "resume";
299 case OHCI_USB_OPER: return "operational";
300 case OHCI_USB_SUSPEND: return "suspend";
301 }
302 return "?";
303 }
304
305 /* dump control and status registers */
306 static void ohci_dump_status (ohci_t *controller)
307 {
308 struct ohci_regs *regs = controller->regs;
309 __u32 temp;
310
311 temp = readl (&regs->revision) & 0xff;
312 if (temp != 0x10)
313 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
314
315 temp = readl (&regs->control);
316 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
317 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
318 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
319 (temp & OHCI_CTRL_IR) ? " IR" : "",
320 hcfs2string (temp & OHCI_CTRL_HCFS),
321 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
322 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
323 (temp & OHCI_CTRL_IE) ? " IE" : "",
324 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
325 temp & OHCI_CTRL_CBSR
326 );
327
328 temp = readl (&regs->cmdstatus);
329 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
330 (temp & OHCI_SOC) >> 16,
331 (temp & OHCI_OCR) ? " OCR" : "",
332 (temp & OHCI_BLF) ? " BLF" : "",
333 (temp & OHCI_CLF) ? " CLF" : "",
334 (temp & OHCI_HCR) ? " HCR" : ""
335 );
336
337 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
338 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
339
340 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
341
342 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
343 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
344
345 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
346 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
347
348 maybe_print_eds ("donehead", readl (&regs->donehead));
349 }
350
351 static void ohci_dump_roothub (ohci_t *controller, int verbose)
352 {
353 __u32 temp, ndp, i;
354
355 temp = roothub_a (controller);
356 ndp = (temp & RH_A_NDP);
357 #ifdef CONFIG_AT91C_PQFP_UHPBUG
358 ndp = (ndp == 2) ? 1:0;
359 #endif
360 if (verbose) {
361 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
362 ((temp & RH_A_POTPGT) >> 24) & 0xff,
363 (temp & RH_A_NOCP) ? " NOCP" : "",
364 (temp & RH_A_OCPM) ? " OCPM" : "",
365 (temp & RH_A_DT) ? " DT" : "",
366 (temp & RH_A_NPS) ? " NPS" : "",
367 (temp & RH_A_PSM) ? " PSM" : "",
368 ndp
369 );
370 temp = roothub_b (controller);
371 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
372 temp,
373 (temp & RH_B_PPCM) >> 16,
374 (temp & RH_B_DR)
375 );
376 temp = roothub_status (controller);
377 dbg ("roothub.status: %08x%s%s%s%s%s%s",
378 temp,
379 (temp & RH_HS_CRWE) ? " CRWE" : "",
380 (temp & RH_HS_OCIC) ? " OCIC" : "",
381 (temp & RH_HS_LPSC) ? " LPSC" : "",
382 (temp & RH_HS_DRWE) ? " DRWE" : "",
383 (temp & RH_HS_OCI) ? " OCI" : "",
384 (temp & RH_HS_LPS) ? " LPS" : ""
385 );
386 }
387
388 for (i = 0; i < ndp; i++) {
389 temp = roothub_portstatus (controller, i);
390 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
391 i,
392 temp,
393 (temp & RH_PS_PRSC) ? " PRSC" : "",
394 (temp & RH_PS_OCIC) ? " OCIC" : "",
395 (temp & RH_PS_PSSC) ? " PSSC" : "",
396 (temp & RH_PS_PESC) ? " PESC" : "",
397 (temp & RH_PS_CSC) ? " CSC" : "",
398
399 (temp & RH_PS_LSDA) ? " LSDA" : "",
400 (temp & RH_PS_PPS) ? " PPS" : "",
401 (temp & RH_PS_PRS) ? " PRS" : "",
402 (temp & RH_PS_POCI) ? " POCI" : "",
403 (temp & RH_PS_PSS) ? " PSS" : "",
404
405 (temp & RH_PS_PES) ? " PES" : "",
406 (temp & RH_PS_CCS) ? " CCS" : ""
407 );
408 }
409 }
410
411 static void ohci_dump (ohci_t *controller, int verbose)
412 {
413 dbg ("OHCI controller usb-%s state", controller->slot_name);
414
415 /* dumps some of the state we know about */
416 ohci_dump_status (controller);
417 if (verbose)
418 ep_print_int_eds (controller, "hcca");
419 dbg ("hcca frame #%04x", controller->hcca->frame_no);
420 ohci_dump_roothub (controller, 1);
421 }
422 #endif /* DEBUG */
423
424 /*-------------------------------------------------------------------------*
425 * Interface functions (URB)
426 *-------------------------------------------------------------------------*/
427
428 /* get a transfer request */
429
430 int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
431 {
432 ohci_t *ohci;
433 ed_t * ed;
434 urb_priv_t *purb_priv = urb;
435 int i, size = 0;
436 struct usb_device *dev = urb->dev;
437 unsigned long pipe = urb->pipe;
438 void *buffer = urb->transfer_buffer;
439 int transfer_len = urb->transfer_buffer_length;
440 int interval = urb->interval;
441
442 ohci = &gohci;
443
444 /* when controller's hung, permit only roothub cleanup attempts
445 * such as powering down ports */
446 if (ohci->disabled) {
447 err("sohci_submit_job: EPIPE");
448 return -1;
449 }
450
451 /* we're about to begin a new transaction here so mark the URB unfinished */
452 urb->finished = 0;
453
454 /* every endpoint has a ed, locate and fill it */
455 if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {
456 err("sohci_submit_job: ENOMEM");
457 return -1;
458 }
459
460 /* for the private part of the URB we need the number of TDs (size) */
461 switch (usb_pipetype (pipe)) {
462 case PIPE_BULK: /* one TD for every 4096 Byte */
463 size = (transfer_len - 1) / 4096 + 1;
464 break;
465 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
466 size = (transfer_len == 0)? 2:
467 (transfer_len - 1) / 4096 + 3;
468 break;
469 case PIPE_INTERRUPT: /* 1 TD */
470 size = 1;
471 break;
472 }
473
474 ed->purb = urb;
475
476 if (size >= (N_URB_TD - 1)) {
477 err("need %d TDs, only have %d", size, N_URB_TD);
478 return -1;
479 }
480 purb_priv->pipe = pipe;
481
482 /* fill the private part of the URB */
483 purb_priv->length = size;
484 purb_priv->ed = ed;
485 purb_priv->actual_length = 0;
486
487 /* allocate the TDs */
488 /* note that td[0] was allocated in ep_add_ed */
489 for (i = 0; i < size; i++) {
490 purb_priv->td[i] = td_alloc (dev);
491 if (!purb_priv->td[i]) {
492 purb_priv->length = i;
493 urb_free_priv (purb_priv);
494 err("sohci_submit_job: ENOMEM");
495 return -1;
496 }
497 }
498
499 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
500 urb_free_priv (purb_priv);
501 err("sohci_submit_job: EINVAL");
502 return -1;
503 }
504
505 /* link the ed into a chain if is not already */
506 if (ed->state != ED_OPER)
507 ep_link (ohci, ed);
508
509 /* fill the TDs and link it to the ed */
510 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
511
512 return 0;
513 }
514
515 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
516 {
517 struct ohci_regs *regs = hc->regs;
518
519 switch (usb_pipetype (urb->pipe)) {
520 case PIPE_INTERRUPT:
521 /* implicitly requeued */
522 if (urb->dev->irq_handle &&
523 (urb->dev->irq_act_len = urb->actual_length)) {
524 writel (OHCI_INTR_WDH, &regs->intrenable);
525 readl (&regs->intrenable); /* PCI posting flush */
526 urb->dev->irq_handle(urb->dev);
527 writel (OHCI_INTR_WDH, &regs->intrdisable);
528 readl (&regs->intrdisable); /* PCI posting flush */
529 }
530 urb->actual_length = 0;
531 td_submit_job (
532 urb->dev,
533 urb->pipe,
534 urb->transfer_buffer,
535 urb->transfer_buffer_length,
536 NULL,
537 urb,
538 urb->interval);
539 break;
540 case PIPE_CONTROL:
541 case PIPE_BULK:
542 break;
543 default:
544 return 0;
545 }
546 return 1;
547 }
548
549 /*-------------------------------------------------------------------------*/
550
551 #ifdef DEBUG
552 /* tell us the current USB frame number */
553
554 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
555 {
556 ohci_t *ohci = &gohci;
557
558 return m16_swap (ohci->hcca->frame_no);
559 }
560 #endif
561
562 /*-------------------------------------------------------------------------*
563 * ED handling functions
564 *-------------------------------------------------------------------------*/
565
566 /* search for the right branch to insert an interrupt ed into the int tree
567 * do some load ballancing;
568 * returns the branch and
569 * sets the interval to interval = 2^integer (ld (interval)) */
570
571 static int ep_int_ballance (ohci_t * ohci, int interval, int load)
572 {
573 int i, branch = 0;
574
575 /* search for the least loaded interrupt endpoint
576 * branch of all 32 branches
577 */
578 for (i = 0; i < 32; i++)
579 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
580 branch = i;
581
582 branch = branch % interval;
583 for (i = branch; i < 32; i += interval)
584 ohci->ohci_int_load [i] += load;
585
586 return branch;
587 }
588
589 /*-------------------------------------------------------------------------*/
590
591 /* 2^int( ld (inter)) */
592
593 static int ep_2_n_interval (int inter)
594 {
595 int i;
596 for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
597 return 1 << i;
598 }
599
600 /*-------------------------------------------------------------------------*/
601
602 /* the int tree is a binary tree
603 * in order to process it sequentially the indexes of the branches have to be mapped
604 * the mapping reverses the bits of a word of num_bits length */
605
606 static int ep_rev (int num_bits, int word)
607 {
608 int i, wout = 0;
609
610 for (i = 0; i < num_bits; i++)
611 wout |= (((word >> i) & 1) << (num_bits - i - 1));
612 return wout;
613 }
614
615 /*-------------------------------------------------------------------------*
616 * ED handling functions
617 *-------------------------------------------------------------------------*/
618
619 /* link an ed into one of the HC chains */
620
621 static int ep_link (ohci_t *ohci, ed_t *edi)
622 {
623 volatile ed_t *ed = edi;
624 int int_branch;
625 int i;
626 int inter;
627 int interval;
628 int load;
629 __u32 * ed_p;
630
631 ed->state = ED_OPER;
632 ed->int_interval = 0;
633
634 switch (ed->type) {
635 case PIPE_CONTROL:
636 ed->hwNextED = 0;
637 if (ohci->ed_controltail == NULL) {
638 writel (ed, &ohci->regs->ed_controlhead);
639 } else {
640 ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);
641 }
642 ed->ed_prev = ohci->ed_controltail;
643 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
644 !ohci->ed_rm_list[1] && !ohci->sleeping) {
645 ohci->hc_control |= OHCI_CTRL_CLE;
646 writel (ohci->hc_control, &ohci->regs->control);
647 }
648 ohci->ed_controltail = edi;
649 break;
650
651 case PIPE_BULK:
652 ed->hwNextED = 0;
653 if (ohci->ed_bulktail == NULL) {
654 writel (ed, &ohci->regs->ed_bulkhead);
655 } else {
656 ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);
657 }
658 ed->ed_prev = ohci->ed_bulktail;
659 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
660 !ohci->ed_rm_list[1] && !ohci->sleeping) {
661 ohci->hc_control |= OHCI_CTRL_BLE;
662 writel (ohci->hc_control, &ohci->regs->control);
663 }
664 ohci->ed_bulktail = edi;
665 break;
666
667 case PIPE_INTERRUPT:
668 load = ed->int_load;
669 interval = ep_2_n_interval (ed->int_period);
670 ed->int_interval = interval;
671 int_branch = ep_int_ballance (ohci, interval, load);
672 ed->int_branch = int_branch;
673
674 for (i = 0; i < ep_rev (6, interval); i += inter) {
675 inter = 1;
676 for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
677 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
678 ed_p = &(((ed_t *)ed_p)->hwNextED))
679 inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
680 ed->hwNextED = *ed_p;
681 *ed_p = m32_swap((unsigned long)ed);
682 }
683 break;
684 }
685 return 0;
686 }
687
688 /*-------------------------------------------------------------------------*/
689
690 /* scan the periodic table to find and unlink this ED */
691 static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,
692 unsigned index, unsigned period)
693 {
694 for (; index < NUM_INTS; index += period) {
695 __u32 *ed_p = &ohci->hcca->int_table [index];
696
697 /* ED might have been unlinked through another path */
698 while (*ed_p != 0) {
699 if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {
700 *ed_p = ed->hwNextED;
701 break;
702 }
703 ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);
704 }
705 }
706 }
707
708 /* unlink an ed from one of the HC chains.
709 * just the link to the ed is unlinked.
710 * the link from the ed still points to another operational ed or 0
711 * so the HC can eventually finish the processing of the unlinked ed */
712
713 static int ep_unlink (ohci_t *ohci, ed_t *edi)
714 {
715 volatile ed_t *ed = edi;
716 int i;
717
718 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
719
720 switch (ed->type) {
721 case PIPE_CONTROL:
722 if (ed->ed_prev == NULL) {
723 if (!ed->hwNextED) {
724 ohci->hc_control &= ~OHCI_CTRL_CLE;
725 writel (ohci->hc_control, &ohci->regs->control);
726 }
727 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
728 } else {
729 ed->ed_prev->hwNextED = ed->hwNextED;
730 }
731 if (ohci->ed_controltail == ed) {
732 ohci->ed_controltail = ed->ed_prev;
733 } else {
734 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
735 }
736 break;
737
738 case PIPE_BULK:
739 if (ed->ed_prev == NULL) {
740 if (!ed->hwNextED) {
741 ohci->hc_control &= ~OHCI_CTRL_BLE;
742 writel (ohci->hc_control, &ohci->regs->control);
743 }
744 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
745 } else {
746 ed->ed_prev->hwNextED = ed->hwNextED;
747 }
748 if (ohci->ed_bulktail == ed) {
749 ohci->ed_bulktail = ed->ed_prev;
750 } else {
751 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
752 }
753 break;
754
755 case PIPE_INTERRUPT:
756 periodic_unlink (ohci, ed, 0, 1);
757 for (i = ed->int_branch; i < 32; i += ed->int_interval)
758 ohci->ohci_int_load[i] -= ed->int_load;
759 break;
760 }
761 ed->state = ED_UNLINK;
762 return 0;
763 }
764
765 /*-------------------------------------------------------------------------*/
766
767 /* add/reinit an endpoint; this should be done once at the
768 * usb_set_configuration command, but the USB stack is a little bit
769 * stateless so we do it at every transaction if the state of the ed
770 * is ED_NEW then a dummy td is added and the state is changed to
771 * ED_UNLINK in all other cases the state is left unchanged the ed
772 * info fields are setted anyway even though most of them should not
773 * change
774 */
775 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,
776 int interval, int load)
777 {
778 td_t *td;
779 ed_t *ed_ret;
780 volatile ed_t *ed;
781
782 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
783 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
784
785 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
786 err("ep_add_ed: pending delete");
787 /* pending delete request */
788 return NULL;
789 }
790
791 if (ed->state == ED_NEW) {
792 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
793 /* dummy td; end of td list for ed */
794 td = td_alloc (usb_dev);
795 ed->hwTailP = m32_swap ((unsigned long)td);
796 ed->hwHeadP = ed->hwTailP;
797 ed->state = ED_UNLINK;
798 ed->type = usb_pipetype (pipe);
799 ohci_dev.ed_cnt++;
800 }
801
802 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
803 | usb_pipeendpoint (pipe) << 7
804 | (usb_pipeisoc (pipe)? 0x8000: 0)
805 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
806 | usb_pipeslow (pipe) << 13
807 | usb_maxpacket (usb_dev, pipe) << 16);
808
809 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
810 ed->int_period = interval;
811 ed->int_load = load;
812 }
813
814 return ed_ret;
815 }
816
817 /*-------------------------------------------------------------------------*
818 * TD handling functions
819 *-------------------------------------------------------------------------*/
820
821 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
822
823 static void td_fill (ohci_t *ohci, unsigned int info,
824 void *data, int len,
825 struct usb_device *dev, int index, urb_priv_t *urb_priv)
826 {
827 volatile td_t *td, *td_pt;
828 #ifdef OHCI_FILL_TRACE
829 int i;
830 #endif
831
832 if (index > urb_priv->length) {
833 err("index > length");
834 return;
835 }
836 /* use this td as the next dummy */
837 td_pt = urb_priv->td [index];
838 td_pt->hwNextTD = 0;
839
840 /* fill the old dummy TD */
841 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
842
843 td->ed = urb_priv->ed;
844 td->next_dl_td = NULL;
845 td->index = index;
846 td->data = (__u32)data;
847 #ifdef OHCI_FILL_TRACE
848 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
849 for (i = 0; i < len; i++)
850 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
851 printf("\n");
852 }
853 #endif
854 if (!len)
855 data = 0;
856
857 td->hwINFO = m32_swap (info);
858 td->hwCBP = m32_swap ((unsigned long)data);
859 if (data)
860 td->hwBE = m32_swap ((unsigned long)(data + len - 1));
861 else
862 td->hwBE = 0;
863 td->hwNextTD = m32_swap ((unsigned long)td_pt);
864
865 /* append to queue */
866 td->ed->hwTailP = td->hwNextTD;
867 }
868
869 /*-------------------------------------------------------------------------*/
870
871 /* prepare all TDs of a transfer */
872
873 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
874 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
875 {
876 ohci_t *ohci = &gohci;
877 int data_len = transfer_len;
878 void *data;
879 int cnt = 0;
880 __u32 info = 0;
881 unsigned int toggle = 0;
882
883 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
884 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
885 toggle = TD_T_TOGGLE;
886 } else {
887 toggle = TD_T_DATA0;
888 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
889 }
890 urb->td_cnt = 0;
891 if (data_len)
892 data = buffer;
893 else
894 data = 0;
895
896 switch (usb_pipetype (pipe)) {
897 case PIPE_BULK:
898 info = usb_pipeout (pipe)?
899 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
900 while(data_len > 4096) {
901 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
902 data += 4096; data_len -= 4096; cnt++;
903 }
904 info = usb_pipeout (pipe)?
905 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
906 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
907 cnt++;
908
909 if (!ohci->sleeping)
910 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
911 break;
912
913 case PIPE_CONTROL:
914 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
915 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
916 if (data_len > 0) {
917 info = usb_pipeout (pipe)?
918 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
919 /* NOTE: mishandles transfers >8K, some >4K */
920 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
921 }
922 info = usb_pipeout (pipe)?
923 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
924 td_fill (ohci, info, data, 0, dev, cnt++, urb);
925 if (!ohci->sleeping)
926 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
927 break;
928
929 case PIPE_INTERRUPT:
930 info = usb_pipeout (urb->pipe)?
931 TD_CC | TD_DP_OUT | toggle:
932 TD_CC | TD_R | TD_DP_IN | toggle;
933 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
934 break;
935 }
936 if (urb->length != cnt)
937 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
938 }
939
940 /*-------------------------------------------------------------------------*
941 * Done List handling functions
942 *-------------------------------------------------------------------------*/
943
944 /* calculate the transfer length and update the urb */
945
946 static void dl_transfer_length(td_t * td)
947 {
948 __u32 tdINFO, tdBE, tdCBP;
949 urb_priv_t *lurb_priv = td->ed->purb;
950
951 tdINFO = m32_swap (td->hwINFO);
952 tdBE = m32_swap (td->hwBE);
953 tdCBP = m32_swap (td->hwCBP);
954
955 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
956 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
957 if (tdBE != 0) {
958 if (td->hwCBP == 0)
959 lurb_priv->actual_length += tdBE - td->data + 1;
960 else
961 lurb_priv->actual_length += tdCBP - td->data;
962 }
963 }
964 }
965
966 /*-------------------------------------------------------------------------*/
967
968 /* replies to the request have to be on a FIFO basis so
969 * we reverse the reversed done-list */
970
971 static td_t * dl_reverse_done_list (ohci_t *ohci)
972 {
973 __u32 td_list_hc;
974 td_t *td_rev = NULL;
975 td_t *td_list = NULL;
976 urb_priv_t *lurb_priv = NULL;
977
978 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
979 ohci->hcca->done_head = 0;
980
981 while (td_list_hc) {
982 td_list = (td_t *)td_list_hc;
983
984 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
985 lurb_priv = td_list->ed->purb;
986 dbg(" USB-error/status: %x : %p",
987 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
988 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
989 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
990 td_list->ed->hwHeadP =
991 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
992 (td_list->ed->hwHeadP & m32_swap (0x2));
993 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
994 } else
995 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
996 }
997 #ifdef CONFIG_MPC5200
998 td_list->hwNextTD = 0;
999 #endif
1000 }
1001
1002 td_list->next_dl_td = td_rev;
1003 td_rev = td_list;
1004 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
1005 }
1006 return td_list;
1007 }
1008
1009 /*-------------------------------------------------------------------------*/
1010
1011 /* td done list */
1012 static int dl_done_list (ohci_t *ohci, td_t *td_list)
1013 {
1014 td_t *td_list_next = NULL;
1015 ed_t *ed;
1016 int cc = 0;
1017 int stat = 0;
1018 /* urb_t *urb; */
1019 urb_priv_t *lurb_priv;
1020 __u32 tdINFO, edHeadP, edTailP;
1021
1022 while (td_list) {
1023 td_list_next = td_list->next_dl_td;
1024
1025 tdINFO = m32_swap (td_list->hwINFO);
1026
1027 ed = td_list->ed;
1028 lurb_priv = ed->purb;
1029
1030 dl_transfer_length(td_list);
1031
1032 /* error code of transfer */
1033 cc = TD_CC_GET (tdINFO);
1034 if (cc != 0) {
1035 dbg("ConditionCode %#x", cc);
1036 stat = cc_to_error[cc];
1037 }
1038
1039 /* see if this done list makes for all TD's of current URB,
1040 * and mark the URB finished if so */
1041 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
1042 #if 1
1043 if ((ed->state & (ED_OPER | ED_UNLINK)) &&
1044 (lurb_priv->state != URB_DEL))
1045 #else
1046 if ((ed->state & (ED_OPER | ED_UNLINK)))
1047 #endif
1048 lurb_priv->finished = sohci_return_job(ohci,
1049 lurb_priv);
1050 else
1051 dbg("dl_done_list: strange.., ED state %x, ed->state\n");
1052 } else
1053 dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
1054 lurb_priv->length);
1055 if (ed->state != ED_NEW &&
1056 (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {
1057 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
1058 edTailP = m32_swap (ed->hwTailP);
1059
1060 /* unlink eds if they are not busy */
1061 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1062 ep_unlink (ohci, ed);
1063 }
1064
1065 td_list = td_list_next;
1066 }
1067 return stat;
1068 }
1069
1070 /*-------------------------------------------------------------------------*
1071 * Virtual Root Hub
1072 *-------------------------------------------------------------------------*/
1073
1074 /* Device descriptor */
1075 static __u8 root_hub_dev_des[] =
1076 {
1077 0x12, /* __u8 bLength; */
1078 0x01, /* __u8 bDescriptorType; Device */
1079 0x10, /* __u16 bcdUSB; v1.1 */
1080 0x01,
1081 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
1082 0x00, /* __u8 bDeviceSubClass; */
1083 0x00, /* __u8 bDeviceProtocol; */
1084 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
1085 0x00, /* __u16 idVendor; */
1086 0x00,
1087 0x00, /* __u16 idProduct; */
1088 0x00,
1089 0x00, /* __u16 bcdDevice; */
1090 0x00,
1091 0x00, /* __u8 iManufacturer; */
1092 0x01, /* __u8 iProduct; */
1093 0x00, /* __u8 iSerialNumber; */
1094 0x01 /* __u8 bNumConfigurations; */
1095 };
1096
1097 /* Configuration descriptor */
1098 static __u8 root_hub_config_des[] =
1099 {
1100 0x09, /* __u8 bLength; */
1101 0x02, /* __u8 bDescriptorType; Configuration */
1102 0x19, /* __u16 wTotalLength; */
1103 0x00,
1104 0x01, /* __u8 bNumInterfaces; */
1105 0x01, /* __u8 bConfigurationValue; */
1106 0x00, /* __u8 iConfiguration; */
1107 0x40, /* __u8 bmAttributes;
1108 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
1109 0x00, /* __u8 MaxPower; */
1110
1111 /* interface */
1112 0x09, /* __u8 if_bLength; */
1113 0x04, /* __u8 if_bDescriptorType; Interface */
1114 0x00, /* __u8 if_bInterfaceNumber; */
1115 0x00, /* __u8 if_bAlternateSetting; */
1116 0x01, /* __u8 if_bNumEndpoints; */
1117 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
1118 0x00, /* __u8 if_bInterfaceSubClass; */
1119 0x00, /* __u8 if_bInterfaceProtocol; */
1120 0x00, /* __u8 if_iInterface; */
1121
1122 /* endpoint */
1123 0x07, /* __u8 ep_bLength; */
1124 0x05, /* __u8 ep_bDescriptorType; Endpoint */
1125 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
1126 0x03, /* __u8 ep_bmAttributes; Interrupt */
1127 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1128 0x00,
1129 0xff /* __u8 ep_bInterval; 255 ms */
1130 };
1131
1132 static unsigned char root_hub_str_index0[] =
1133 {
1134 0x04, /* __u8 bLength; */
1135 0x03, /* __u8 bDescriptorType; String-descriptor */
1136 0x09, /* __u8 lang ID */
1137 0x04, /* __u8 lang ID */
1138 };
1139
1140 static unsigned char root_hub_str_index1[] =
1141 {
1142 28, /* __u8 bLength; */
1143 0x03, /* __u8 bDescriptorType; String-descriptor */
1144 'O', /* __u8 Unicode */
1145 0, /* __u8 Unicode */
1146 'H', /* __u8 Unicode */
1147 0, /* __u8 Unicode */
1148 'C', /* __u8 Unicode */
1149 0, /* __u8 Unicode */
1150 'I', /* __u8 Unicode */
1151 0, /* __u8 Unicode */
1152 ' ', /* __u8 Unicode */
1153 0, /* __u8 Unicode */
1154 'R', /* __u8 Unicode */
1155 0, /* __u8 Unicode */
1156 'o', /* __u8 Unicode */
1157 0, /* __u8 Unicode */
1158 'o', /* __u8 Unicode */
1159 0, /* __u8 Unicode */
1160 't', /* __u8 Unicode */
1161 0, /* __u8 Unicode */
1162 ' ', /* __u8 Unicode */
1163 0, /* __u8 Unicode */
1164 'H', /* __u8 Unicode */
1165 0, /* __u8 Unicode */
1166 'u', /* __u8 Unicode */
1167 0, /* __u8 Unicode */
1168 'b', /* __u8 Unicode */
1169 0, /* __u8 Unicode */
1170 };
1171
1172 /* Hub class-specific descriptor is constructed dynamically */
1173
1174 /*-------------------------------------------------------------------------*/
1175
1176 #define OK(x) len = (x); break
1177 #ifdef DEBUG
1178 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
1179 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
1180 #else
1181 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
1182 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
1183 #endif
1184 #define RD_RH_STAT roothub_status(&gohci)
1185 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
1186
1187 /* request to virtual root hub */
1188
1189 int rh_check_port_status(ohci_t *controller)
1190 {
1191 __u32 temp, ndp, i;
1192 int res;
1193
1194 res = -1;
1195 temp = roothub_a (controller);
1196 ndp = (temp & RH_A_NDP);
1197 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1198 ndp = (ndp == 2) ? 1:0;
1199 #endif
1200 for (i = 0; i < ndp; i++) {
1201 temp = roothub_portstatus (controller, i);
1202 /* check for a device disconnect */
1203 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1204 (RH_PS_PESC | RH_PS_CSC)) &&
1205 ((temp & RH_PS_CCS) == 0)) {
1206 res = i;
1207 break;
1208 }
1209 }
1210 return res;
1211 }
1212
1213 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1214 void *buffer, int transfer_len, struct devrequest *cmd)
1215 {
1216 void * data = buffer;
1217 int leni = transfer_len;
1218 int len = 0;
1219 int stat = 0;
1220 __u32 datab[4];
1221 __u8 *data_buf = (__u8 *)datab;
1222 __u16 bmRType_bReq;
1223 __u16 wValue;
1224 __u16 wIndex;
1225 __u16 wLength;
1226
1227 #ifdef DEBUG
1228 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1229 #else
1230 wait_ms(1);
1231 #endif
1232 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1233 info("Root-Hub submit IRQ: NOT implemented");
1234 return 0;
1235 }
1236
1237 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1238 wValue = cpu_to_le16 (cmd->value);
1239 wIndex = cpu_to_le16 (cmd->index);
1240 wLength = cpu_to_le16 (cmd->length);
1241
1242 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1243 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1244
1245 switch (bmRType_bReq) {
1246 /* Request Destination:
1247 without flags: Device,
1248 RH_INTERFACE: interface,
1249 RH_ENDPOINT: endpoint,
1250 RH_CLASS means HUB here,
1251 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1252 */
1253
1254 case RH_GET_STATUS:
1255 *(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
1256 case RH_GET_STATUS | RH_INTERFACE:
1257 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1258 case RH_GET_STATUS | RH_ENDPOINT:
1259 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1260 case RH_GET_STATUS | RH_CLASS:
1261 *(__u32 *) data_buf = cpu_to_le32 (
1262 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1263 OK (4);
1264 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1265 *(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
1266
1267 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1268 switch (wValue) {
1269 case (RH_ENDPOINT_STALL): OK (0);
1270 }
1271 break;
1272
1273 case RH_CLEAR_FEATURE | RH_CLASS:
1274 switch (wValue) {
1275 case RH_C_HUB_LOCAL_POWER:
1276 OK(0);
1277 case (RH_C_HUB_OVER_CURRENT):
1278 WR_RH_STAT(RH_HS_OCIC); OK (0);
1279 }
1280 break;
1281
1282 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1283 switch (wValue) {
1284 case (RH_PORT_ENABLE):
1285 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1286 case (RH_PORT_SUSPEND):
1287 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1288 case (RH_PORT_POWER):
1289 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1290 case (RH_C_PORT_CONNECTION):
1291 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1292 case (RH_C_PORT_ENABLE):
1293 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1294 case (RH_C_PORT_SUSPEND):
1295 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1296 case (RH_C_PORT_OVER_CURRENT):
1297 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1298 case (RH_C_PORT_RESET):
1299 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1300 }
1301 break;
1302
1303 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1304 switch (wValue) {
1305 case (RH_PORT_SUSPEND):
1306 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1307 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1308 if (RD_RH_PORTSTAT & RH_PS_CCS)
1309 WR_RH_PORTSTAT (RH_PS_PRS);
1310 OK (0);
1311 case (RH_PORT_POWER):
1312 WR_RH_PORTSTAT (RH_PS_PPS );
1313 wait_ms(100);
1314 OK (0);
1315 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1316 if (RD_RH_PORTSTAT & RH_PS_CCS)
1317 WR_RH_PORTSTAT (RH_PS_PES );
1318 OK (0);
1319 }
1320 break;
1321
1322 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1323
1324 case RH_GET_DESCRIPTOR:
1325 switch ((wValue & 0xff00) >> 8) {
1326 case (0x01): /* device descriptor */
1327 len = min_t(unsigned int,
1328 leni,
1329 min_t(unsigned int,
1330 sizeof (root_hub_dev_des),
1331 wLength));
1332 data_buf = root_hub_dev_des; OK(len);
1333 case (0x02): /* configuration descriptor */
1334 len = min_t(unsigned int,
1335 leni,
1336 min_t(unsigned int,
1337 sizeof (root_hub_config_des),
1338 wLength));
1339 data_buf = root_hub_config_des; OK(len);
1340 case (0x03): /* string descriptors */
1341 if(wValue==0x0300) {
1342 len = min_t(unsigned int,
1343 leni,
1344 min_t(unsigned int,
1345 sizeof (root_hub_str_index0),
1346 wLength));
1347 data_buf = root_hub_str_index0;
1348 OK(len);
1349 }
1350 if(wValue==0x0301) {
1351 len = min_t(unsigned int,
1352 leni,
1353 min_t(unsigned int,
1354 sizeof (root_hub_str_index1),
1355 wLength));
1356 data_buf = root_hub_str_index1;
1357 OK(len);
1358 }
1359 default:
1360 stat = USB_ST_STALLED;
1361 }
1362 break;
1363
1364 case RH_GET_DESCRIPTOR | RH_CLASS:
1365 {
1366 __u32 temp = roothub_a (&gohci);
1367
1368 data_buf [0] = 9; /* min length; */
1369 data_buf [1] = 0x29;
1370 data_buf [2] = temp & RH_A_NDP;
1371 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1372 data_buf [2] = (data_buf [2] == 2) ? 1:0;
1373 #endif
1374 data_buf [3] = 0;
1375 if (temp & RH_A_PSM) /* per-port power switching? */
1376 data_buf [3] |= 0x1;
1377 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1378 data_buf [3] |= 0x10;
1379 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1380 data_buf [3] |= 0x8;
1381
1382 /* corresponds to data_buf[4-7] */
1383 datab [1] = 0;
1384 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1385 temp = roothub_b (&gohci);
1386 data_buf [7] = temp & RH_B_DR;
1387 if (data_buf [2] < 7) {
1388 data_buf [8] = 0xff;
1389 } else {
1390 data_buf [0] += 2;
1391 data_buf [8] = (temp & RH_B_DR) >> 8;
1392 data_buf [10] = data_buf [9] = 0xff;
1393 }
1394
1395 len = min_t(unsigned int, leni,
1396 min_t(unsigned int, data_buf [0], wLength));
1397 OK (len);
1398 }
1399
1400 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1401
1402 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1403
1404 default:
1405 dbg ("unsupported root hub command");
1406 stat = USB_ST_STALLED;
1407 }
1408
1409 #ifdef DEBUG
1410 ohci_dump_roothub (&gohci, 1);
1411 #else
1412 wait_ms(1);
1413 #endif
1414
1415 len = min_t(int, len, leni);
1416 if (data != data_buf)
1417 memcpy (data, data_buf, len);
1418 dev->act_len = len;
1419 dev->status = stat;
1420
1421 #ifdef DEBUG
1422 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1423 #else
1424 wait_ms(1);
1425 #endif
1426
1427 return stat;
1428 }
1429
1430 /*-------------------------------------------------------------------------*/
1431
1432 /* common code for handling submit messages - used for all but root hub */
1433 /* accesses. */
1434 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1435 int transfer_len, struct devrequest *setup, int interval)
1436 {
1437 int stat = 0;
1438 int maxsize = usb_maxpacket(dev, pipe);
1439 int timeout;
1440 urb_priv_t *urb;
1441
1442 urb = malloc(sizeof(urb_priv_t));
1443 memset(urb, 0, sizeof(urb_priv_t));
1444
1445 urb->dev = dev;
1446 urb->pipe = pipe;
1447 urb->transfer_buffer = buffer;
1448 urb->transfer_buffer_length = transfer_len;
1449 urb->interval = interval;
1450
1451 /* device pulled? Shortcut the action. */
1452 if (devgone == dev) {
1453 dev->status = USB_ST_CRC_ERR;
1454 return 0;
1455 }
1456
1457 #ifdef DEBUG
1458 urb->actual_length = 0;
1459 pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1460 #else
1461 wait_ms(1);
1462 #endif
1463 if (!maxsize) {
1464 err("submit_common_message: pipesize for pipe %lx is zero",
1465 pipe);
1466 return -1;
1467 }
1468
1469 if (sohci_submit_job(urb, setup) < 0) {
1470 err("sohci_submit_job failed");
1471 return -1;
1472 }
1473
1474 #if 0
1475 wait_ms(10);
1476 /* ohci_dump_status(&gohci); */
1477 #endif
1478
1479 /* allow more time for a BULK device to react - some are slow */
1480 #define BULK_TO 5000 /* timeout in milliseconds */
1481 if (usb_pipetype (pipe) == PIPE_BULK)
1482 timeout = BULK_TO;
1483 else
1484 timeout = 100;
1485
1486 /* wait for it to complete */
1487 for (;;) {
1488 /* check whether the controller is done */
1489 stat = hc_interrupt();
1490 if (stat < 0) {
1491 stat = USB_ST_CRC_ERR;
1492 break;
1493 }
1494
1495 /* NOTE: since we are not interrupt driven in U-Boot and always
1496 * handle only one URB at a time, we cannot assume the
1497 * transaction finished on the first successful return from
1498 * hc_interrupt().. unless the flag for current URB is set,
1499 * meaning that all TD's to/from device got actually
1500 * transferred and processed. If the current URB is not
1501 * finished we need to re-iterate this loop so as
1502 * hc_interrupt() gets called again as there needs to be some
1503 * more TD's to process still */
1504 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1505 /* 0xff is returned for an SF-interrupt */
1506 break;
1507 }
1508
1509 if (--timeout) {
1510 wait_ms(1);
1511 if (!urb->finished)
1512 dbg("\%");
1513
1514 } else {
1515 err("CTL:TIMEOUT ");
1516 dbg("submit_common_msg: TO status %x\n", stat);
1517 urb->finished = 1;
1518 stat = USB_ST_CRC_ERR;
1519 break;
1520 }
1521 }
1522
1523 dev->status = stat;
1524 dev->act_len = transfer_len;
1525
1526 #ifdef DEBUG
1527 pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1528 #else
1529 wait_ms(1);
1530 #endif
1531
1532 /* free TDs in urb_priv */
1533 if (usb_pipetype (pipe) != PIPE_INTERRUPT)
1534 urb_free_priv (urb);
1535 return 0;
1536 }
1537
1538 /* submit routines called from usb.c */
1539 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1540 int transfer_len)
1541 {
1542 info("submit_bulk_msg");
1543 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1544 }
1545
1546 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1547 int transfer_len, struct devrequest *setup)
1548 {
1549 int maxsize = usb_maxpacket(dev, pipe);
1550
1551 info("submit_control_msg");
1552 #ifdef DEBUG
1553 pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1554 #else
1555 wait_ms(1);
1556 #endif
1557 if (!maxsize) {
1558 err("submit_control_message: pipesize for pipe %lx is zero",
1559 pipe);
1560 return -1;
1561 }
1562 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1563 gohci.rh.dev = dev;
1564 /* root hub - redirect */
1565 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1566 setup);
1567 }
1568
1569 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1570 }
1571
1572 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1573 int transfer_len, int interval)
1574 {
1575 info("submit_int_msg");
1576 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
1577 interval);
1578 }
1579
1580 /*-------------------------------------------------------------------------*
1581 * HC functions
1582 *-------------------------------------------------------------------------*/
1583
1584 /* reset the HC and BUS */
1585
1586 static int hc_reset (ohci_t *ohci)
1587 {
1588 int timeout = 30;
1589 int smm_timeout = 50; /* 0,5 sec */
1590
1591 dbg("%s\n", __FUNCTION__);
1592
1593 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1594 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1595 info("USB HC TakeOver from SMM");
1596 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1597 wait_ms (10);
1598 if (--smm_timeout == 0) {
1599 err("USB HC TakeOver failed!");
1600 return -1;
1601 }
1602 }
1603 }
1604
1605 /* Disable HC interrupts */
1606 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1607
1608 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1609 ohci->slot_name,
1610 readl(&ohci->regs->control));
1611
1612 /* Reset USB (needed by some controllers) */
1613 ohci->hc_control = 0;
1614 writel (ohci->hc_control, &ohci->regs->control);
1615
1616 /* HC Reset requires max 10 us delay */
1617 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1618 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1619 if (--timeout == 0) {
1620 err("USB HC reset timed out!");
1621 return -1;
1622 }
1623 udelay (1);
1624 }
1625 return 0;
1626 }
1627
1628 /*-------------------------------------------------------------------------*/
1629
1630 /* Start an OHCI controller, set the BUS operational
1631 * enable interrupts
1632 * connect the virtual root hub */
1633
1634 static int hc_start (ohci_t * ohci)
1635 {
1636 __u32 mask;
1637 unsigned int fminterval;
1638
1639 ohci->disabled = 1;
1640
1641 /* Tell the controller where the control and bulk lists are
1642 * The lists are empty now. */
1643
1644 writel (0, &ohci->regs->ed_controlhead);
1645 writel (0, &ohci->regs->ed_bulkhead);
1646
1647 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1648
1649 fminterval = 0x2edf;
1650 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1651 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1652 writel (fminterval, &ohci->regs->fminterval);
1653 writel (0x628, &ohci->regs->lsthresh);
1654
1655 /* start controller operations */
1656 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1657 ohci->disabled = 0;
1658 writel (ohci->hc_control, &ohci->regs->control);
1659
1660 /* disable all interrupts */
1661 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1662 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1663 OHCI_INTR_OC | OHCI_INTR_MIE);
1664 writel (mask, &ohci->regs->intrdisable);
1665 /* clear all interrupts */
1666 mask &= ~OHCI_INTR_MIE;
1667 writel (mask, &ohci->regs->intrstatus);
1668 /* Choose the interrupts we care about now - but w/o MIE */
1669 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1670 writel (mask, &ohci->regs->intrenable);
1671
1672 #ifdef OHCI_USE_NPS
1673 /* required for AMD-756 and some Mac platforms */
1674 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1675 &ohci->regs->roothub.a);
1676 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1677 #endif /* OHCI_USE_NPS */
1678
1679 #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1680 /* POTPGT delay is bits 24-31, in 2 ms units. */
1681 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1682
1683 /* connect the virtual root hub */
1684 ohci->rh.devnum = 0;
1685
1686 return 0;
1687 }
1688
1689 /*-------------------------------------------------------------------------*/
1690
1691 /* Poll USB interrupt. */
1692 void usb_event_poll(void)
1693 {
1694 hc_interrupt();
1695 }
1696
1697 /* an interrupt happens */
1698
1699 static int hc_interrupt (void)
1700 {
1701 ohci_t *ohci = &gohci;
1702 struct ohci_regs *regs = ohci->regs;
1703 int ints;
1704 int stat = -1;
1705
1706 if ((ohci->hcca->done_head != 0) &&
1707 !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1708 ints = OHCI_INTR_WDH;
1709 } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1710 ohci->disabled++;
1711 err ("%s device removed!", ohci->slot_name);
1712 return -1;
1713 } else if ((ints &= readl (&regs->intrenable)) == 0) {
1714 dbg("hc_interrupt: returning..\n");
1715 return 0xff;
1716 }
1717
1718 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1719
1720 if (ints & OHCI_INTR_RHSC) {
1721 got_rhsc = 1;
1722 stat = 0xff;
1723 }
1724
1725 if (ints & OHCI_INTR_UE) {
1726 ohci->disabled++;
1727 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1728 ohci->slot_name);
1729 /* e.g. due to PCI Master/Target Abort */
1730
1731 #ifdef DEBUG
1732 ohci_dump (ohci, 1);
1733 #else
1734 wait_ms(1);
1735 #endif
1736 /* FIXME: be optimistic, hope that bug won't repeat often. */
1737 /* Make some non-interrupt context restart the controller. */
1738 /* Count and limit the retries though; either hardware or */
1739 /* software errors can go forever... */
1740 hc_reset (ohci);
1741 return -1;
1742 }
1743
1744 if (ints & OHCI_INTR_WDH) {
1745 wait_ms(1);
1746 writel (OHCI_INTR_WDH, &regs->intrdisable);
1747 (void)readl (&regs->intrdisable); /* flush */
1748 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1749 writel (OHCI_INTR_WDH, &regs->intrenable);
1750 (void)readl (&regs->intrdisable); /* flush */
1751 }
1752
1753 if (ints & OHCI_INTR_SO) {
1754 dbg("USB Schedule overrun\n");
1755 writel (OHCI_INTR_SO, &regs->intrenable);
1756 stat = -1;
1757 }
1758
1759 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1760 if (ints & OHCI_INTR_SF) {
1761 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1762 wait_ms(1);
1763 writel (OHCI_INTR_SF, &regs->intrdisable);
1764 if (ohci->ed_rm_list[frame] != NULL)
1765 writel (OHCI_INTR_SF, &regs->intrenable);
1766 stat = 0xff;
1767 }
1768
1769 writel (ints, &regs->intrstatus);
1770 return stat;
1771 }
1772
1773 /*-------------------------------------------------------------------------*/
1774
1775 /*-------------------------------------------------------------------------*/
1776
1777 /* De-allocate all resources.. */
1778
1779 static void hc_release_ohci (ohci_t *ohci)
1780 {
1781 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1782
1783 if (!ohci->disabled)
1784 hc_reset (ohci);
1785 }
1786
1787 /*-------------------------------------------------------------------------*/
1788
1789 /*
1790 * low level initalisation routine, called from usb.c
1791 */
1792 static char ohci_inited = 0;
1793
1794 int usb_lowlevel_init(void)
1795 {
1796 #ifdef CONFIG_PCI_OHCI
1797 pci_dev_t pdev;
1798 #endif
1799
1800 #ifdef CFG_USB_OHCI_CPU_INIT
1801 /* cpu dependant init */
1802 if(usb_cpu_init())
1803 return -1;
1804 #endif
1805
1806 #ifdef CFG_USB_OHCI_BOARD_INIT
1807 /* board dependant init */
1808 if(usb_board_init())
1809 return -1;
1810 #endif
1811 memset (&gohci, 0, sizeof (ohci_t));
1812
1813 /* align the storage */
1814 if ((__u32)&ghcca[0] & 0xff) {
1815 err("HCCA not aligned!!");
1816 return -1;
1817 }
1818 phcca = &ghcca[0];
1819 info("aligned ghcca %p", phcca);
1820 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1821 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1822 err("EDs not aligned!!");
1823 return -1;
1824 }
1825 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1826 if ((__u32)gtd & 0x7) {
1827 err("TDs not aligned!!");
1828 return -1;
1829 }
1830 ptd = gtd;
1831 gohci.hcca = phcca;
1832 memset (phcca, 0, sizeof (struct ohci_hcca));
1833
1834 gohci.disabled = 1;
1835 gohci.sleeping = 0;
1836 gohci.irq = -1;
1837 #ifdef CONFIG_PCI_OHCI
1838 pdev = pci_find_devices(ohci_pci_ids, 0);
1839
1840 if (pdev != -1) {
1841 u16 vid, did;
1842 u32 base;
1843 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1844 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1845 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1846 vid, did, (pdev >> 16) & 0xff,
1847 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1848 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1849 printf("OHCI regs address 0x%08x\n", base);
1850 gohci.regs = (struct ohci_regs *)base;
1851 } else
1852 return -1;
1853 #else
1854 gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
1855 #endif
1856
1857 gohci.flags = 0;
1858 gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
1859
1860 if (hc_reset (&gohci) < 0) {
1861 hc_release_ohci (&gohci);
1862 err ("can't reset usb-%s", gohci.slot_name);
1863 #ifdef CFG_USB_OHCI_BOARD_INIT
1864 /* board dependant cleanup */
1865 usb_board_init_fail();
1866 #endif
1867
1868 #ifdef CFG_USB_OHCI_CPU_INIT
1869 /* cpu dependant cleanup */
1870 usb_cpu_init_fail();
1871 #endif
1872 return -1;
1873 }
1874
1875 /* FIXME this is a second HC reset; why?? */
1876 /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1877 wait_ms(10); */
1878 if (hc_start (&gohci) < 0) {
1879 err ("can't start usb-%s", gohci.slot_name);
1880 hc_release_ohci (&gohci);
1881 /* Initialization failed */
1882 #ifdef CFG_USB_OHCI_BOARD_INIT
1883 /* board dependant cleanup */
1884 usb_board_stop();
1885 #endif
1886
1887 #ifdef CFG_USB_OHCI_CPU_INIT
1888 /* cpu dependant cleanup */
1889 usb_cpu_stop();
1890 #endif
1891 return -1;
1892 }
1893
1894 #ifdef DEBUG
1895 ohci_dump (&gohci, 1);
1896 #else
1897 wait_ms(1);
1898 #endif
1899 ohci_inited = 1;
1900 return 0;
1901 }
1902
1903 int usb_lowlevel_stop(void)
1904 {
1905 /* this gets called really early - before the controller has */
1906 /* even been initialized! */
1907 if (!ohci_inited)
1908 return 0;
1909 /* TODO release any interrupts, etc. */
1910 /* call hc_release_ohci() here ? */
1911 hc_reset (&gohci);
1912
1913 #ifdef CFG_USB_OHCI_BOARD_INIT
1914 /* board dependant cleanup */
1915 if(usb_board_stop())
1916 return -1;
1917 #endif
1918
1919 #ifdef CFG_USB_OHCI_CPU_INIT
1920 /* cpu dependant cleanup */
1921 if(usb_cpu_stop())
1922 return -1;
1923 #endif
1924
1925 return 0;
1926 }
1927 #endif /* CONFIG_USB_OHCI_NEW */
Fork of the u-boot for for Samsung based MINI2440 board