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config-gta02v5-beyond.patch
[u-boot-openmoko/mini2440.git] / drivers / block / ata_piix.c
blob441a4dcd8d652f1aface989268f72bacaf39360c
1 /*
2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 * with the reference to ata_piix driver in kernel 2.4.32
22 */
23
24 /*
25 * This file contains SATA controller and SATA drive initialization functions
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <pci.h>
31 #include <command.h>
32 #include <config.h>
33 #include <asm/byteorder.h>
34 #include <part.h>
35 #include <ide.h>
36 #include <ata.h>
37
38 #ifdef CFG_ATA_PIIX /*ata_piix driver */
39
40 extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE];
41 extern int curr_device;
42
43 #define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
44
45 #define SATA_DECL
46 #define DRV_DECL /*For file specific declarations */
47 #include "ata_piix.h"
48
49 /*Macros realted to PCI*/
50 #define PCI_SATA_BUS 0x00
51 #define PCI_SATA_DEV 0x1f
52 #define PCI_SATA_FUNC 0x02
53
54 #define PCI_SATA_BASE1 0x10
55 #define PCI_SATA_BASE2 0x14
56 #define PCI_SATA_BASE3 0x18
57 #define PCI_SATA_BASE4 0x1c
58 #define PCI_SATA_BASE5 0x20
59 #define PCI_PMR 0x90
60 #define PCI_PI 0x09
61 #define PCI_PCS 0x92
62 #define PCI_DMA_CTL 0x48
63
64 #define PORT_PRESENT (1<<0)
65 #define PORT_ENABLED (1<<4)
66
67 u32 bdf;
68 u32 iobase1 = 0; /*Primary cmd block */
69 u32 iobase2 = 0; /*Primary ctl block */
70 u32 iobase3 = 0; /*Sec cmd block */
71 u32 iobase4 = 0; /*sec ctl block */
72 u32 iobase5 = 0; /*BMDMA*/
73 int
74 pci_sata_init (void)
75 {
76 u32 bus = PCI_SATA_BUS;
77 u32 dev = PCI_SATA_DEV;
78 u32 fun = PCI_SATA_FUNC;
79 u16 cmd = 0;
80 u8 lat = 0, pcibios_max_latency = 0xff;
81 u8 pmr; /*Port mapping reg */
82 u8 pi; /*Prgming Interface reg */
83
84 bdf = PCI_BDF (bus, dev, fun);
85 pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
86 pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
87 pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
88 pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
89 pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
90
91 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
92 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
93 (iobase5 == 0xFFFFFFFF)) {
94 printf ("error no base addr for SATA controller\n");
95 return 1;
96 /*ERROR*/}
97
98 iobase1 &= 0xFFFFFFFE;
99 iobase2 &= 0xFFFFFFFE;
100 iobase3 &= 0xFFFFFFFE;
101 iobase4 &= 0xFFFFFFFE;
102 iobase5 &= 0xFFFFFFFE;
103
104 /*check for mode */
105 pci_read_config_byte (bdf, PCI_PMR, &pmr);
106 if (pmr > 1) {
107 printf ("combined mode not supported\n");
108 return 1;
109 }
110
111 pci_read_config_byte (bdf, PCI_PI, &pi);
112 if ((pi & 0x05) != 0x05) {
113 printf ("Sata is in Legacy mode\n");
114 return 1;
115 } else {
116 printf ("sata is in Native mode\n");
117 }
118
119 /*MASTER CFG AND IO CFG */
120 pci_read_config_word (bdf, PCI_COMMAND, &cmd);
121 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
122 pci_write_config_word (bdf, PCI_COMMAND, cmd);
123 pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
124
125 if (lat < 16)
126 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
127 else if (lat > pcibios_max_latency)
128 lat = pcibios_max_latency;
129 pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
130
131 return 0;
132 }
133
134 int
135 sata_bus_probe (int port_no)
136 {
137 int orig_mask, mask;
138 u16 pcs;
139
140 mask = (PORT_PRESENT << port_no);
141 pci_read_config_word (bdf, PCI_PCS, &pcs);
142 orig_mask = (int) pcs & 0xff;
143 if ((orig_mask & mask) != mask)
144 return 0;
145 else
146 return 1;
147 }
148
149 int
150 init_sata (int dev)
151 {
152 static int done = 0;
153 u8 i, rv = 0;
154
155 if (!done)
156 done = 1;
157 else
158 return 0;
159
160 rv = pci_sata_init ();
161 if (rv == 1) {
162 printf ("pci initialization failed\n");
163 return 1;
164 }
165
166 port[0].port_no = 0;
167 port[0].ioaddr.cmd_addr = iobase1;
168 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
169 iobase2 | ATA_PCI_CTL_OFS;
170 port[0].ioaddr.bmdma_addr = iobase5;
171
172 port[1].port_no = 1;
173 port[1].ioaddr.cmd_addr = iobase3;
174 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
175 iobase4 | ATA_PCI_CTL_OFS;
176 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
177
178 for (i = 0; i < CFG_SATA_MAXBUS; i++)
179 sata_port (&port[i].ioaddr);
180
181 for (i = 0; i < CFG_SATA_MAXBUS; i++) {
182 if (!(sata_bus_probe (i))) {
183 port[i].port_state = 0;
184 printf ("SATA#%d port is not present \n", i);
185 } else {
186 printf ("SATA#%d port is present\n", i);
187 if (sata_bus_softreset (i)) {
188 port[i].port_state = 0;
189 } else {
190 port[i].port_state = 1;
191 }
192 }
193 }
194
195 for (i = 0; i < CFG_SATA_MAXBUS; i++) {
196 u8 j, devno;
197
198 if (port[i].port_state == 0)
199 continue;
200 for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
201 sata_identify (i, j);
202 set_Feature_cmd (i, j);
203 devno = i * CFG_SATA_DEVS_PER_BUS + j;
204 if ((sata_dev_desc[devno].lba > 0) &&
205 (sata_dev_desc[devno].blksz > 0)) {
206 dev_print (&sata_dev_desc[devno]);
207 /* initialize partition type */
208 init_part (&sata_dev_desc[devno]);
209 if (curr_device < 0)
210 curr_device =
211 i * CFG_SATA_DEVS_PER_BUS + j;
212 }
213 }
214 }
215 return 0;
216 }
217
218 static u8 __inline__
219 sata_inb (unsigned long ioaddr)
220 {
221 return inb (ioaddr);
222 }
223
224 static void __inline__
225 sata_outb (unsigned char val, unsigned long ioaddr)
226 {
227 outb (val, ioaddr);
228 }
229
230 static void
231 output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
232 {
233 outsw (ioaddr->data_addr, sect_buf, words << 1);
234 }
235
236 static int
237 input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
238 {
239 insw (ioaddr->data_addr, sect_buf, words << 1);
240 return 0;
241 }
242
243 static void
244 sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
245 {
246 unsigned char *end, *last;
247
248 last = dst;
249 end = src + len - 1;
250
251 /* reserve space for '\0' */
252 if (len < 2)
253 goto OUT;
254
255 /* skip leading white space */
256 while ((*src) && (src < end) && (*src == ' '))
257 ++src;
258
259 /* copy string, omitting trailing white space */
260 while ((*src) && (src < end)) {
261 *dst++ = *src;
262 if (*src++ != ' ')
263 last = dst;
264 }
265 OUT:
266 *last = '\0';
267 }
268
269 int
270 sata_bus_softreset (int num)
271 {
272 u8 dev = 0, status = 0, i;
273
274 port[num].dev_mask = 0;
275
276 for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) {
277 if (!(sata_devchk (&port[num].ioaddr, i))) {
278 PRINTF ("dev_chk failed for dev#%d\n", i);
279 } else {
280 port[num].dev_mask |= (1 << i);
281 PRINTF ("dev_chk passed for dev#%d\n", i);
282 }
283 }
284
285 if (!(port[num].dev_mask)) {
286 printf ("no devices on port%d\n", num);
287 return 1;
288 }
289
290 dev_select (&port[num].ioaddr, dev);
291
292 port[num].ctl_reg = 0x08; /*Default value of control reg */
293 sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
294 udelay (10);
295 sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
296 udelay (10);
297 sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
298
299 /* spec mandates ">= 2ms" before checking status.
300 * We wait 150ms, because that was the magic delay used for
301 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
302 * between when the ATA command register is written, and then
303 * status is checked. Because waiting for "a while" before
304 * checking status is fine, post SRST, we perform this magic
305 * delay here as well.
306 */
307 msleep (150);
308 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
309 while ((status & ATA_BUSY)) {
310 msleep (100);
311 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
312 }
313
314 if (status & ATA_BUSY)
315 printf ("ata%u is slow to respond,plz be patient\n", port);
316
317 while ((status & ATA_BUSY)) {
318 msleep (100);
319 status = sata_chk_status (&port[num].ioaddr);
320 }
321
322 if (status & ATA_BUSY) {
323 printf ("ata%u failed to respond : ", port);
324 printf ("bus reset failed\n");
325 return 1;
326 }
327 return 0;
328 }
329
330 void
331 sata_identify (int num, int dev)
332 {
333 u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev;
334 u16 iobuf[ATA_SECT_SIZE];
335 u64 n_sectors = 0;
336 u8 mask = 0;
337
338 memset (iobuf, 0, sizeof (iobuf));
339 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
340
341 if (dev == 0)
342 mask = 0x01;
343 else
344 mask = 0x02;
345
346 if (!(port[num].dev_mask & mask)) {
347 printf ("dev%d is not present on port#%d\n", dev, num);
348 return;
349 }
350
351 printf ("port=%d dev=%d\n", num, dev);
352
353 dev_select (&port[num].ioaddr, dev);
354
355 status = 0;
356 cmd = ATA_CMD_IDENT; /*Device Identify Command */
357 sata_outb (cmd, port[num].ioaddr.command_addr);
358 sata_inb (port[num].ioaddr.altstatus_addr);
359 udelay (10);
360
361 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
362 if (status & ATA_ERR) {
363 printf ("\ndevice not responding\n");
364 port[num].dev_mask &= ~mask;
365 return;
366 }
367
368 input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
369
370 PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
371 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
372 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
373 iobuf[87], iobuf[88]);
374
375 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
376 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
377 PRINTF ("ata%u: no dma/lba\n", num);
378 }
379 ata_dump_id (iobuf);
380
381 if (ata_id_has_lba48 (iobuf)) {
382 n_sectors = ata_id_u64 (iobuf, 100);
383 } else {
384 n_sectors = ata_id_u32 (iobuf, 60);
385 }
386 PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
387 PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
388
389 if (n_sectors == 0) {
390 port[num].dev_mask &= ~mask;
391 return;
392 }
393
394 sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
395 sizeof (sata_dev_desc[devno].revision));
396 sata_cpy (sata_dev_desc[devno].vendor, iop->model,
397 sizeof (sata_dev_desc[devno].vendor));
398 sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
399 sizeof (sata_dev_desc[devno].product));
400 strswab (sata_dev_desc[devno].revision);
401 strswab (sata_dev_desc[devno].vendor);
402
403 if ((iop->config & 0x0080) == 0x0080) {
404 sata_dev_desc[devno].removable = 1;
405 } else {
406 sata_dev_desc[devno].removable = 0;
407 }
408
409 sata_dev_desc[devno].lba = iop->lba_capacity;
410 PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
411
412 #ifdef CONFIG_LBA48
413 if (iop->command_set_2 & 0x0400) {
414 sata_dev_desc[devno].lba48 = 1;
415 lba = (unsigned long long) iop->lba48_capacity[0] |
416 ((unsigned long long) iop->lba48_capacity[1] << 16) |
417 ((unsigned long long) iop->lba48_capacity[2] << 32) |
418 ((unsigned long long) iop->lba48_capacity[3] << 48);
419 } else {
420 sata_dev_desc[devno].lba48 = 0;
421 }
422 #endif
423
424 /* assuming HD */
425 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
426 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
427 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
428 }
429
430 void
431 set_Feature_cmd (int num, int dev)
432 {
433 u8 mask = 0x00, status = 0;
434
435 if (dev == 0)
436 mask = 0x01;
437 else
438 mask = 0x02;
439
440 if (!(port[num].dev_mask & mask)) {
441 PRINTF ("dev%d is not present on port#%d\n", dev, num);
442 return;
443 }
444
445 dev_select (&port[num].ioaddr, dev);
446
447 sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
448 sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
449 sata_outb (0, port[num].ioaddr.lbal_addr);
450 sata_outb (0, port[num].ioaddr.lbam_addr);
451 sata_outb (0, port[num].ioaddr.lbah_addr);
452
453 sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
454 sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
455
456 udelay (50);
457 msleep (150);
458
459 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
460 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
461 printf ("Error : status 0x%02x\n", status);
462 port[num].dev_mask &= ~mask;
463 }
464 }
465
466 void
467 sata_port (struct sata_ioports *ioport)
468 {
469 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
470 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
471 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
472 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
473 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
474 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
475 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
476 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
477 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
478 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
479 }
480
481 int
482 sata_devchk (struct sata_ioports *ioaddr, int dev)
483 {
484 u8 nsect, lbal;
485
486 dev_select (ioaddr, dev);
487
488 sata_outb (0x55, ioaddr->nsect_addr);
489 sata_outb (0xaa, ioaddr->lbal_addr);
490
491 sata_outb (0xaa, ioaddr->nsect_addr);
492 sata_outb (0x55, ioaddr->lbal_addr);
493
494 sata_outb (0x55, ioaddr->nsect_addr);
495 sata_outb (0xaa, ioaddr->lbal_addr);
496
497 nsect = sata_inb (ioaddr->nsect_addr);
498 lbal = sata_inb (ioaddr->lbal_addr);
499
500 if ((nsect == 0x55) && (lbal == 0xaa))
501 return 1; /* we found a device */
502 else
503 return 0; /* nothing found */
504 }
505
506 void
507 dev_select (struct sata_ioports *ioaddr, int dev)
508 {
509 u8 tmp = 0;
510
511 if (dev == 0)
512 tmp = ATA_DEVICE_OBS;
513 else
514 tmp = ATA_DEVICE_OBS | ATA_DEV1;
515
516 sata_outb (tmp, ioaddr->device_addr);
517 sata_inb (ioaddr->altstatus_addr);
518 udelay (5);
519 }
520
521 u8
522 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
523 {
524 u8 status;
525
526 do {
527 udelay (1000);
528 status = sata_chk_status (ioaddr);
529 max--;
530 } while ((status & bits) && (max > 0));
531
532 return status;
533 }
534
535 u8
536 sata_chk_status (struct sata_ioports * ioaddr)
537 {
538 return sata_inb (ioaddr->status_addr);
539 }
540
541 void
542 msleep (int count)
543 {
544 int i;
545
546 for (i = 0; i < count; i++)
547 udelay (1000);
548 }
549
550 ulong
551 sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
552 {
553 ulong n = 0, *buffer = (ulong *)buff;
554 u8 dev = 0, num = 0, mask = 0, status = 0;
555
556 #ifdef CONFIG_LBA48
557 unsigned char lba48 = 0;
558
559 if (blknr & 0x0000fffff0000000) {
560 if (!sata_dev_desc[devno].lba48) {
561 printf ("Drive doesn't support 48-bit addressing\n");
562 return 0;
563 }
564 /* more than 28 bits used, use 48bit mode */
565 lba48 = 1;
566 }
567 #endif
568 /*Port Number */
569 num = device / CFG_SATA_DEVS_PER_BUS;
570 /*dev on the port */
571 if (device >= CFG_SATA_DEVS_PER_BUS)
572 dev = device - CFG_SATA_DEVS_PER_BUS;
573 else
574 dev = device;
575
576 if (dev == 0)
577 mask = 0x01;
578 else
579 mask = 0x02;
580
581 if (!(port[num].dev_mask & mask)) {
582 printf ("dev%d is not present on port#%d\n", dev, num);
583 return 0;
584 }
585
586 /* Select device */
587 dev_select (&port[num].ioaddr, dev);
588
589 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
590 if (status & ATA_BUSY) {
591 printf ("ata%u failed to respond\n", port[num].port_no);
592 return n;
593 }
594 while (blkcnt-- > 0) {
595 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
596 if (status & ATA_BUSY) {
597 printf ("ata%u failed to respond\n", 0);
598 return n;
599 }
600 #ifdef CONFIG_LBA48
601 if (lba48) {
602 /* write high bits */
603 sata_outb (0, port[num].ioaddr.nsect_addr);
604 sata_outb ((blknr >> 24) & 0xFF,
605 port[num].ioaddr.lbal_addr);
606 sata_outb ((blknr >> 32) & 0xFF,
607 port[num].ioaddr.lbam_addr);
608 sata_outb ((blknr >> 40) & 0xFF,
609 port[num].ioaddr.lbah_addr);
610 }
611 #endif
612 sata_outb (1, port[num].ioaddr.nsect_addr);
613 sata_outb (((blknr) >> 0) & 0xFF,
614 port[num].ioaddr.lbal_addr);
615 sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
616 sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
617
618 #ifdef CONFIG_LBA48
619 if (lba48) {
620 sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
621 sata_outb (ATA_CMD_READ_EXT,
622 port[num].ioaddr.command_addr);
623 } else
624 #endif
625 {
626 sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
627 port[num].ioaddr.device_addr);
628 sata_outb (ATA_CMD_READ,
629 port[num].ioaddr.command_addr);
630 }
631
632 msleep (50);
633 /*may take up to 4 sec */
634 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
635
636 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
637 != ATA_STAT_DRQ) {
638 u8 err = 0;
639
640 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
641 device, (ulong) blknr, status);
642 err = sata_inb (port[num].ioaddr.error_addr);
643 printf ("Error reg = 0x%x\n", err);
644 return (n);
645 }
646 input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
647 sata_inb (port[num].ioaddr.altstatus_addr);
648 udelay (50);
649
650 ++n;
651 ++blknr;
652 buffer += ATA_SECTORWORDS;
653 }
654 return n;
655 }
656
657 ulong
658 sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
659 {
660 ulong n = 0, *buffer = (ulong *)buff;
661 unsigned char status = 0, num = 0, dev = 0, mask = 0;
662
663 #ifdef CONFIG_LBA48
664 unsigned char lba48 = 0;
665
666 if (blknr & 0x0000fffff0000000) {
667 if (!sata_dev_desc[devno].lba48) {
668 printf ("Drive doesn't support 48-bit addressing\n");
669 return 0;
670 }
671 /* more than 28 bits used, use 48bit mode */
672 lba48 = 1;
673 }
674 #endif
675 /*Port Number */
676 num = device / CFG_SATA_DEVS_PER_BUS;
677 /*dev on the Port */
678 if (device >= CFG_SATA_DEVS_PER_BUS)
679 dev = device - CFG_SATA_DEVS_PER_BUS;
680 else
681 dev = device;
682
683 if (dev == 0)
684 mask = 0x01;
685 else
686 mask = 0x02;
687
688 /* Select device */
689 dev_select (&port[num].ioaddr, dev);
690
691 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
692 if (status & ATA_BUSY) {
693 printf ("ata%u failed to respond\n", port[num].port_no);
694 return n;
695 }
696
697 while (blkcnt-- > 0) {
698 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
699 if (status & ATA_BUSY) {
700 printf ("ata%u failed to respond\n",
701 port[num].port_no);
702 return n;
703 }
704 #ifdef CONFIG_LBA48
705 if (lba48) {
706 /* write high bits */
707 sata_outb (0, port[num].ioaddr.nsect_addr);
708 sata_outb ((blknr >> 24) & 0xFF,
709 port[num].ioaddr.lbal_addr);
710 sata_outb ((blknr >> 32) & 0xFF,
711 port[num].ioaddr.lbam_addr);
712 sata_outb ((blknr >> 40) & 0xFF,
713 port[num].ioaddr.lbah_addr);
714 }
715 #endif
716 sata_outb (1, port[num].ioaddr.nsect_addr);
717 sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
718 sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
719 sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
720 #ifdef CONFIG_LBA48
721 if (lba48) {
722 sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
723 sata_outb (ATA_CMD_WRITE_EXT,
724 port[num].ioaddr.command_addr);
725 } else
726 #endif
727 {
728 sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
729 port[num].ioaddr.device_addr);
730 sata_outb (ATA_CMD_WRITE,
731 port[num].ioaddr.command_addr);
732 }
733
734 msleep (50);
735 /*may take up to 4 sec */
736 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
737 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
738 != ATA_STAT_DRQ) {
739 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
740 device, (ulong) blknr, status);
741 return (n);
742 }
743
744 output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
745 sata_inb (port[num].ioaddr.altstatus_addr);
746 udelay (50);
747
748 ++n;
749 ++blknr;
750 buffer += ATA_SECTORWORDS;
751 }
752 return n;
753 }
754
755 int scan_sata(int dev)
756 {
757 return 0;
758 }
759
760 #endif
Fork of the u-boot for for Samsung based MINI2440 board