include/configs/zeus.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * zeus.h - configuration for Zeus board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_ZEUS             1               /* Board is Zeus        */
  34 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  35 #define CONFIG_405EP            1               /* Specifc 405EP support*/
  36
  37 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  38
  39 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  40 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  41
  42 #define PLLMR0_DEFAULT          PLLMR0_333_111_55_111
  43 #define PLLMR1_DEFAULT          PLLMR1_333_111_55_111
  44
  45 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  46
  47 #define CONFIG_OVERWRITE_ETHADDR_ONCE   1
  48
  49 #define CONFIG_MII              1       /* MII PHY management           */
  50 #define CONFIG_PHY_ADDR         0x01    /* PHY address                  */
  51 #define CONFIG_HAS_ETH1         1
  52 #define CONFIG_PHY1_ADDR        0x11    /* EMAC1 PHY address            */
  53 #define CONFIG_NET_MULTI        1
  54 #define CFG_RX_ETH_BUFFER       16      /* Number of ethernet rx buffers & descriptors */
  55 #define CONFIG_PHY_RESET        1
  56 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_BOOTFILESIZE
  62 #define CONFIG_BOOTP_BOOTPATH
  63 #define CONFIG_BOOTP_GATEWAY
  64 #define CONFIG_BOOTP_HOSTNAME
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #include <config_cmd_default.h>
  70
  71 #define CONFIG_CMD_ASKENV
  72 #define CONFIG_CMD_CACHE
  73 #define CONFIG_CMD_DHCP
  74 #define CONFIG_CMD_DIAG
  75 #define CONFIG_CMD_EEPROM
  76 #define CONFIG_CMD_ELF
  77 #define CONFIG_CMD_I2C
  78 #define CONFIG_CMD_IRQ
  79 #define CONFIG_CMD_LOG
  80 #define CONFIG_CMD_MII
  81 #define CONFIG_CMD_NET
  82 #define CONFIG_CMD_NFS
  83 #define CONFIG_CMD_PING
  84 #define CONFIG_CMD_REGINFO
  85
  86 /* POST support */
  87 #define CONFIG_POST             (CFG_POST_MEMORY   | \
  88                                  CFG_POST_CPU      | \
  89                                  CFG_POST_CACHE    | \
  90                                  CFG_POST_UART     | \
  91                                  CFG_POST_ETHER)
  92
  93 #define CFG_POST_ETHER_EXT_LOOPBACK     /* eth POST using ext loopack connector */
  94
  95 /* Define here the base-addresses of the UARTs to test in POST */
  96 #define CFG_POST_UART_TABLE     {UART0_BASE}
  97
  98 #define CONFIG_LOGBUFFER
  99 #define CFG_POST_CACHE_ADDR     0x00800000 /* free virtual address      */
 100
 101 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 102
 103 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 104
 105 /*-----------------------------------------------------------------------
 106  * SDRAM
 107  *----------------------------------------------------------------------*/
 108 /*
 109  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 110  */
 111 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
 112 #define CONFIG_SDRAM_BANK1      1       /* init onboard SDRAM bank 1 */
 113
 114 /* SDRAM timings used in datasheet */
 115 #define CFG_SDRAM_CL            3       /* CAS latency */
 116 #define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
 117 #define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
 118 #define CFG_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
 119 #define CFG_SDRAM_tRFC          66      /* Auto refresh period */
 120
 121 /*-----------------------------------------------------------------------
 122  * Serial Port
 123  *----------------------------------------------------------------------*/
 124 #undef  CFG_EXT_SERIAL_CLOCK                    /* external serial clock */
 125 #define CFG_BASE_BAUD           691200
 126 #define CONFIG_BAUDRATE         115200
 127 #define CONFIG_SERIAL_MULTI
 128
 129 /* The following table includes the supported baudrates */
 130 #define CFG_BAUDRATE_TABLE      \
 131         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 132
 133 /*-----------------------------------------------------------------------
 134  * Miscellaneous configurable options
 135  *----------------------------------------------------------------------*/
 136 #define CFG_LONGHELP                    /* undef to save memory         */
 137 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 138 #if defined(CONFIG_CMD_KGDB)
 139 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 140 #else
 141 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 142 #endif
 143 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 144 #define CFG_MAXARGS             16      /* max number of command args   */
 145 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 146
 147 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 148 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 149
 150 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 151 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 152
 153 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 154
 155 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 156 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 157
 158 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 159 #define CONFIG_LOOPW            1       /* enable loopw command         */
 160 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 161 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 162 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 163
 164 /*-----------------------------------------------------------------------
 165  * I2C
 166  *----------------------------------------------------------------------*/
 167 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 168 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 169 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 170 #define CFG_I2C_SLAVE           0x7F
 171
 172 /* these are for the ST M24C02 2kbit serial i2c eeprom */
 173 #define CFG_I2C_EEPROM_ADDR     0x50            /* base address */
 174 #define CFG_I2C_EEPROM_ADDR_LEN 1               /* bytes of address */
 175 /* mask of address bits that overflow into the "EEPROM chip address"    */
 176 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 177
 178 #define CFG_EEPROM_PAGE_WRITE_ENABLE    1       /* write eeprom in pages */
 179 #define CFG_EEPROM_PAGE_WRITE_BITS      3       /* 8 byte write page size */
 180 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 181
 182 /*
 183  * The layout of the I2C EEPROM, used for bootstrap setup and for board-
 184  * specific values, like ethaddr... that can be restored via the sw-reset
 185  * button
 186  */
 187 #define FACTORY_RESET_I2C_EEPROM        0x50
 188 #define FACTORY_RESET_ENV_OFFS          0x80
 189 #define FACTORY_RESET_ENV_SIZE          0x80
 190
 191 /*-----------------------------------------------------------------------
 192  * Start addresses for the final memory configuration
 193  * (Set up by the startup code)
 194  * Please note that CFG_SDRAM_BASE _must_ start at 0
 195  */
 196 #define CFG_SDRAM_BASE          0x00000000
 197 #define CFG_FLASH_BASE          0xFF000000
 198 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 199 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 200 #define CFG_MONITOR_BASE        (-CFG_MONITOR_LEN)
 201
 202 /*
 203  * For booting Linux, the board info and command line data
 204  * have to be in the first 8 MB of memory, since this is
 205  * the maximum mapped by the Linux kernel during initialization.
 206  */
 207 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 208
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 213 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 214
 215 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 216
 217 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 218 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 219
 220 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 221 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 222
 223 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 224 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection        */
 225
 226 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 227 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 228
 229 #ifdef CFG_ENV_IS_IN_FLASH
 230 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector          */
 231 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 232 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 233
 234 /* Address and size of Redundant Environment Sector     */
 235 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 236 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 237 #endif
 238
 239 /*-----------------------------------------------------------------------
 240  * Definitions for initial stack pointer and data area (in data cache)
 241  */
 242 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 243 #define CFG_TEMP_STACK_OCM      1
 244
 245 /* On Chip Memory location */
 246 #define CFG_OCM_DATA_ADDR       0xF8000000
 247 #define CFG_OCM_DATA_SIZE       0x1000
 248 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of OCM              */
 249 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 250
 251 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
 252 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 253 /* reserve some memory for POST and BOOT limit info */
 254 #define CFG_INIT_SP_OFFSET      (CFG_GBL_DATA_OFFSET - 16)
 255
 256 /* extra data in OCM */
 257 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 4)
 258 #define CFG_POST_MAGIC          (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
 259 #define CFG_POST_VAL            (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
 260
 261 /*-----------------------------------------------------------------------
 262  * External Bus Controller (EBC) Setup
 263  */
 264
 265 /* Memory Bank 0 (Flash 16M) initialization                                     */
 266 #define CFG_EBC_PB0AP           0x05815600
 267 #define CFG_EBC_PB0CR           0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */
 268
 269 /*-----------------------------------------------------------------------
 270  * Definitions for GPIO setup (PPC405EP specific)
 271  *
 272  * GPIO0[0]     - External Bus Controller BLAST output
 273  * GPIO0[1-9]   - Instruction trace outputs
 274  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 275  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 276  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 277  * GPIO0[24-27] - UART0 control signal inputs/outputs
 278  * GPIO0[28-29] - UART1 data signal input/output
 279  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 280  */
 281 #define CFG_GPIO0_OSRH          0x15555550      /* Chip selects */
 282 #define CFG_GPIO0_OSRL          0x00000110      /* UART_DTR-pin 27 alt out */
 283 #define CFG_GPIO0_ISR1H         0x10000041      /* Pin 2, 12 is input */
 284 #define CFG_GPIO0_ISR1L         0x15505440      /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
 285 #define CFG_GPIO0_TSRH          0x00000000
 286 #define CFG_GPIO0_TSRL          0x00000000
 287 #define CFG_GPIO0_TCR           0xBFF68317      /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
 288 #define CFG_GPIO0_ODR           0x00000000
 289
 290 #define CFG_GPIO_SW_RESET       1
 291 #define CFG_GPIO_ZEUS_PE        12
 292 #define CFG_GPIO_LED_RED        22
 293 #define CFG_GPIO_LED_GREEN      23
 294
 295 /* Time in milli-seconds */
 296 #define CFG_TIME_POST           5000
 297 #define CFG_TIME_FACTORY_RESET  10000
 298
 299 /*
 300  * Internal Definitions
 301  *
 302  * Boot Flags
 303  */
 304 #define BOOTFLAG_COLD           0x01            /* Normal Power-On: Boot from FLASH     */
 305 #define BOOTFLAG_WARM           0x02            /* Software reboot                      */
 306
 307 #if defined(CONFIG_CMD_KGDB)
 308 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 309 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 310 #endif
 311
 312 /* ENVIRONMENT VARS */
 313
 314 #define CONFIG_PREBOOT          "echo;echo Welcome to Bulletendpoints board v1.1;echo"
 315 #define CONFIG_IPADDR           192.168.1.10
 316 #define CONFIG_SERVERIP         192.168.1.100
 317 #define CONFIG_GATEWAYIP        192.168.1.100
 318 #define CONFIG_ETHADDR          50:00:00:00:06:00
 319 #define CONFIG_ETH1ADDR         50:00:00:00:06:01
 320 #if 0
 321 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled        */
 322 #else
 323 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 324 #endif
 325
 326 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 327         "logversion=2\0"                                                \
 328         "hostname=zeus\0"                                               \
 329         "netdev=eth0\0"                                                 \
 330         "ethact=ppc_4xx_eth0\0"                                         \
 331         "netmask=255.255.255.0\0"                                       \
 332         "ramdisk_size=50000\0"                                          \
 333         "nfsargs=setenv bootargs root=/dev/nfs rw"                      \
 334                 " nfsroot=${serverip}:${rootpath}\0"                    \
 335         "ramargs=setenv bootargs root=/dev/ram rw"                      \
 336                 " ramdisk_size=${ramdisk_size}\0"                       \
 337         "addip=setenv bootargs ${bootargs} "                            \
 338                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 339                 ":${hostname}:${netdev}:off panic=1\0"                  \
 340         "addtty=setenv bootargs ${bootargs} console=ttyS0,"             \
 341                 "${baudrate}\0"                                         \
 342         "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};"               \
 343                 "run nfsargs addip addtty;bootm\0"                      \
 344         "net_ram=tftp ${kernel_mem_addr} ${file_kernel};"               \
 345                 "tftp ${ramdisk_mem_addr} ${file_fs};"                  \
 346                 "run ramargs addip addtty;"                             \
 347                 "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0"        \
 348         "rootpath=/target_fs/zeus\0"                                    \
 349         "kernel_fl_addr=ff000000\0"                                     \
 350         "kernel_mem_addr=200000\0"                                      \
 351         "ramdisk_fl_addr=ff300000\0"                                    \
 352         "ramdisk_mem_addr=4000000\0"                                    \
 353         "uboot_fl_addr=fffc0000\0"                                      \
 354         "uboot_mem_addr=100000\0"                                       \
 355         "file_uboot=/zeus/u-boot.bin\0"                                 \
 356         "tftp_uboot=tftp 100000 ${file_uboot}\0"                        \
 357         "update_uboot=protect off fffc0000 ffffffff;"                   \
 358                 "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;"     \
 359                 "protect on fffc0000 ffffffff\0"                        \
 360         "upd_uboot=run tftp_uboot;run update_uboot\0"                   \
 361         "file_kernel=/zeus/uImage_ba\0"                                 \
 362         "tftp_kernel=tftp 100000 ${file_kernel}\0"                      \
 363         "update_kernel=protect off ff000000 ff17ffff;"                  \
 364                 "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0"   \
 365         "upd_kernel=run tftp_kernel;run update_kernel\0"                \
 366         "file_fs=/zeus/rootfs_ba.img\0"                                 \
 367         "tftp_fs=tftp 100000 ${file_fs}\0"                              \
 368         "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
 369                 "cp.b 100000 ff300000 580000\0"                         \
 370         "upd_fs=run tftp_fs;run update_fs\0"                            \
 371         "bootcmd=chkreset;run ramargs addip addtty addmisc;"            \
 372                 "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0"          \
 373         ""
 374
 375 #endif  /* __CONFIG_H */