include/configs/xupv2p.h

   1 /*
   2  * (C) Copyright 2007 Michal Simek
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #include "../board/xilinx/xupv2p/xparameters.h"
  29
  30 #define CONFIG_MICROBLAZE       1       /* MicroBlaze CPU */
  31 #define CONFIG_XUPV2P           1
  32
  33 /* uart */
  34 #define CONFIG_XILINX_UARTLITE
  35 #define CONFIG_SERIAL_BASE      XILINX_UART_BASEADDR
  36 #define CONFIG_BAUDRATE         XILINX_UART_BAUDRATE
  37 #define CFG_BAUDRATE_TABLE      { CONFIG_BAUDRATE }
  38
  39 /* ethernet */
  40 #define CONFIG_EMAC     1
  41 #define XPAR_EMAC_0_DEVICE_ID   XPAR_XEMAC_NUM_INSTANCES
  42
  43 /*
  44  * setting reset address
  45  *
  46  * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
  47  * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
  48  * to FLASH memory and after loading bitstream jump to FLASH.
  49  * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
  50  * jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
  51  */
  52 /* #define      CFG_RESET_ADDRESS       0x36000000 */
  53
  54 /* gpio */
  55 #ifdef XILINX_GPIO_BASEADDR
  56 #define CFG_GPIO_0              1
  57 #define CFG_GPIO_0_ADDR         XILINX_GPIO_BASEADDR
  58 #endif
  59
  60 /* interrupt controller */
  61 #define CFG_INTC_0              1
  62 #define CFG_INTC_0_ADDR         XILINX_INTC_BASEADDR
  63 #define CFG_INTC_0_NUM          XILINX_INTC_NUM_INTR_INPUTS
  64
  65 /* timer */
  66 #define CFG_TIMER_0             1
  67 #define CFG_TIMER_0_ADDR        XILINX_TIMER_BASEADDR
  68 #define CFG_TIMER_0_IRQ         XILINX_TIMER_IRQ
  69 #define FREQUENCE               XILINX_CLOCK_FREQ
  70 #define CFG_TIMER_0_PRELOAD     ( FREQUENCE/1000 )
  71 #define CONFIG_XILINX_CLOCK_FREQ        XILINX_CLOCK_FREQ
  72
  73 /*
  74  * memory layout - Example
  75  * TEXT_BASE = 0x3600_0000;
  76  * CFG_SRAM_BASE = 0x3000_0000;
  77  * CFG_SRAM_SIZE = 0x1000_0000;
  78  *
  79  * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
  80  * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
  81  * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
  82  *
  83  * 0x3000_0000  CFG_SDRAM_BASE
  84  *                                      FREE
  85  * 0x3600_0000  TEXT_BASE
  86  *              U-BOOT code
  87  * 0x3602_0000
  88  *                                      FREE
  89  *
  90  *                                      STACK
  91  * 0x3FF7_F000  CFG_MALLOC_BASE
  92  *                                      MALLOC_AREA     256kB   Alloc
  93  * 0x3FFB_F000  CFG_MONITOR_BASE
  94  *                                      MONITOR_CODE    256kB   Env
  95  * 0x3FFF_F000  CFG_GBL_DATA_OFFSET
  96  *                                      GLOBAL_DATA     4kB     bd, gd
  97  * 0x4000_0000  CFG_SDRAM_BASE + CFG_SDRAM_SIZE
  98  */
  99
 100 /* ddr sdram - main memory */
 101 #define CFG_SDRAM_BASE          XILINX_RAM_START
 102 #define CFG_SDRAM_SIZE          XILINX_RAM_SIZE
 103 #define CFG_MEMTEST_START       CFG_SDRAM_BASE
 104 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + 0x1000)
 105
 106 /* global pointer */
 107 #define CFG_GBL_DATA_SIZE       0x1000  /* size of global data */
 108 #define CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
 109
 110 /* monitor code */
 111 #define SIZE                    0x40000
 112 #define CFG_MONITOR_LEN         SIZE
 113 #define CFG_MONITOR_BASE        (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
 114 #define CFG_MONITOR_END         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 115 #define CFG_MALLOC_LEN          SIZE
 116 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 117
 118 /* stack */
 119 #define CFG_INIT_SP_OFFSET      CFG_MALLOC_BASE
 120
 121 #define CFG_NO_FLASH            1
 122 #define CFG_ENV_IS_NOWHERE      1
 123 #define CFG_ENV_SIZE            0x1000
 124 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - CFG_ENV_SIZE)
 125
 126 /*
 127  * BOOTP options
 128  */
 129 #define CONFIG_BOOTP_BOOTFILESIZE
 130 #define CONFIG_BOOTP_BOOTPATH
 131 #define CONFIG_BOOTP_GATEWAY
 132 #define CONFIG_BOOTP_HOSTNAME
 133
 134 /*
 135  * Command line configuration.
 136  */
 137 #include <config_cmd_default.h>
 138
 139 #undef CONFIG_CMD_FLASH
 140 #undef CONFIG_CMD_IMLS
 141
 142 #define CONFIG_CMD_ASKENV
 143 #define CONFIG_CMD_CACHE
 144 #define CONFIG_CMD_IRQ
 145 #define CONFIG_CMD_PING
 146
 147 #ifdef XILINX_SYSACE_BASEADDR
 148 #define CONFIG_CMD_EXT2
 149 #define CONFIG_CMD_FAT
 150 #endif
 151
 152 /* Miscellaneous configurable options */
 153 #define CFG_PROMPT      "U-Boot-mONStR> "
 154 #define CFG_CBSIZE      512     /* size of console buffer */
 155 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
 156 #define CFG_MAXARGS     15      /* max number of command args */
 157 #define CFG_LONGHELP
 158 #define CFG_LOAD_ADDR   0x12000000 /* default load address */
 159
 160 #define CONFIG_BOOTDELAY        30
 161 #define CONFIG_BOOTARGS         "root=romfs"
 162 #define CONFIG_HOSTNAME         "xupv2p"
 163 #define CONFIG_BOOTCOMMAND      "base 0;tftp 11000000 image.img;bootm"
 164 #define CONFIG_IPADDR           192.168.0.3
 165 #define CONFIG_SERVERIP         192.168.0.5
 166 #define CONFIG_GATEWAYIP        192.168.0.1
 167 #define CONFIG_ETHADDR          00:E0:0C:00:00:FD
 168
 169 /* architecture dependent code */
 170 #define CFG_USR_EXCEP   /* user exception */
 171 #define CFG_HZ  1000
 172
 173 #define CONFIG_PREBOOT  "echo U-BOOT by mONStR;"        \
 174         "base 0;" \
 175         "echo"
 176
 177 /* system ace */
 178 #ifdef XILINX_SYSACE_BASEADDR
 179 #define CONFIG_SYSTEMACE
 180 /* #define DEBUG_SYSTEMACE */
 181 #define SYSTEMACE_CONFIG_FPGA
 182 #define CFG_SYSTEMACE_BASE      XILINX_SYSACE_BASEADDR
 183 #define CFG_SYSTEMACE_WIDTH     XILINX_SYSACE_MEM_WIDTH
 184 #define CONFIG_DOS_PARTITION
 185 #endif
 186
 187 #endif  /* __CONFIG_H */