include/configs/spieval.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  40 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  41
  42 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  43
  44 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  45 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  46
  47 /*
  48  * Serial console configuration
  49  */
  50 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
  51 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  52 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  53
  54 #ifdef CONFIG_STK52XX
  55 #undef CONFIG_PS2KBD                    /* AT-PS/2 Keyboard             */
  56 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
  57 #define CONFIG_PS2SERIAL        6       /* .. on PSC6                   */
  58 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
  59 #define CONFIG_BOARD_EARLY_INIT_R
  60 #endif /* CONFIG_STK52XX */
  61
  62 /*
  63  * PCI Mapping:
  64  * 0x40000000 - 0x4fffffff - PCI Memory
  65  * 0x50000000 - 0x50ffffff - PCI IO Space
  66  */
  67 #ifdef CONFIG_STK52XX
  68 #define CONFIG_PCI              1
  69 #define CONFIG_PCI_PNP          1
  70 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  71
  72 #define CONFIG_PCI_MEM_BUS      0x40000000
  73 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  74 #define CONFIG_PCI_MEM_SIZE     0x10000000
  75
  76 #define CONFIG_PCI_IO_BUS       0x50000000
  77 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  78 #define CONFIG_PCI_IO_SIZE      0x01000000
  79
  80 #define CONFIG_NET_MULTI        1
  81 #define CONFIG_EEPRO100         1
  82 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  83 #define CONFIG_NS8382X          1
  84 #endif  /* CONFIG_STK52XX */
  85
  86 /*
  87  * Video console
  88  */
  89 #if 1
  90 #define CONFIG_VIDEO
  91 #define CONFIG_VIDEO_SM501
  92 #define CONFIG_VIDEO_SM501_32BPP
  93 #define CONFIG_CFB_CONSOLE
  94 #define CONFIG_VIDEO_LOGO
  95 #define CONFIG_VGA_AS_SINGLE_DEVICE
  96 #define CONFIG_CONSOLE_EXTRA_INFO
  97 #define CONFIG_VIDEO_SW_CURSOR
  98 #define CONFIG_SPLASH_SCREEN
  99 #define CFG_CONSOLE_IS_IN_ENV
 100 #endif
 101
 102 /* Partitions */
 103 #define CONFIG_MAC_PARTITION
 104 #define CONFIG_DOS_PARTITION
 105 #define CONFIG_ISO_PARTITION
 106
 107 /* USB */
 108 #ifdef CONFIG_STK52XX
 109 #define CONFIG_USB_OHCI
 110 #define CONFIG_USB_STORAGE
 111 #endif
 112
 113 /* POST support */
 114 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 115                                  CFG_POST_CPU      | \
 116                                  CFG_POST_I2C)
 117
 118 #ifdef CONFIG_POST
 119 /* preserve space for the post_word at end of on-chip SRAM */
 120 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 121 #endif
 122
 123
 124 /*
 125  * BOOTP options
 126  */
 127 #define CONFIG_BOOTP_BOOTFILESIZE
 128 #define CONFIG_BOOTP_BOOTPATH
 129 #define CONFIG_BOOTP_GATEWAY
 130 #define CONFIG_BOOTP_HOSTNAME
 131
 132
 133 /*
 134  * Command line configuration.
 135  */
 136 #include <config_cmd_default.h>
 137
 138 #define CONFIG_CMD_ASKENV
 139 #define CONFIG_CMD_DATE
 140 #define CONFIG_CMD_DHCP
 141 #define CONFIG_CMD_ECHO
 142 #define CONFIG_CMD_EEPROM
 143 #define CONFIG_CMD_I2C
 144 #define CONFIG_CMD_MII
 145 #define CONFIG_CMD_NFS
 146 #define CONFIG_CMD_PING
 147 #define CONFIG_CMD_REGINFO
 148 #define CONFIG_CMD_SNTP
 149
 150 #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
 151     #define CONFIG_CMD_IDE
 152     #define CONFIG_CMD_FAT
 153     #define CONFIG_CMD_EXT2
 154 #endif
 155
 156 #ifdef CONFIG_STK52XX
 157     #define CONFIG_CMD_USB
 158     #define CONFIG_CMD_FAT
 159 #endif
 160
 161 #ifdef CONFIG_VIDEO
 162     #define CONFIG_CMD_BMP
 163 #endif
 164
 165 #ifdef CONFIG_PCI
 166     #define CONFIG_CMD_PCI
 167 #endif
 168
 169 #ifdef CONFIG_POST
 170 #define CONFIG_CMD_DIAG
 171 #endif
 172
 173
 174 #define CONFIG_TIMESTAMP                /* display image timestamps */
 175
 176 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 177 #   define CFG_LOWBOOT          1
 178 #endif
 179
 180 /*
 181  * Autobooting
 182  */
 183 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 184
 185 #define CONFIG_PREBOOT  "echo;" \
 186         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 187         "echo"
 188
 189 #undef  CONFIG_BOOTARGS
 190
 191 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 192         "netdev=eth0\0"                                                 \
 193         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 194         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 195         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 196                 "nfsroot=${serverip}:${rootpath}\0"                     \
 197         "addip=setenv bootargs ${bootargs} "                            \
 198                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 199                 ":${hostname}:${netdev}:off panic=1\0"                  \
 200         "flash_self=run ramargs addip;"                                 \
 201                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 202         "flash_nfs=run nfsargs addip;"                                  \
 203                 "bootm ${kernel_addr}\0"                                \
 204         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 205         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 206         "load=tftp 200000 ${u-boot}\0"                                  \
 207         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 208         "update=protect off FC000000 FC05FFFF;"                         \
 209                 "erase FC000000 FC05FFFF;"                              \
 210                 "cp.b 200000 FC000000 ${filesize};"                     \
 211                 "protect on FC000000 FC05FFFF\0"                        \
 212         ""
 213
 214 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 215
 216 /*
 217  * IPB Bus clocking configuration.
 218  */
 219 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 220
 221 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 222 /*
 223  * PCI Bus clocking configuration
 224  *
 225  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 226  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 227  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 228  */
 229 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 230 #endif
 231
 232 /*
 233  * I2C configuration
 234  */
 235 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 236 #ifdef CONFIG_TQM5200_REV100
 237 #define CFG_I2C_MODULE          1       /* Select I2C module #1 for rev. 100 board */
 238 #else
 239 #define CFG_I2C_MODULE          2       /* Select I2C module #2 for all other revs */
 240 #endif
 241
 242 /*
 243  * I2C clock frequency
 244  *
 245  * Please notice, that the resulting clock frequency could differ from the
 246  * configured value. This is because the I2C clock is derived from system
 247  * clock over a frequency divider with only a few divider values. U-boot
 248  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 249  * approximation allways lies below the configured value, never above.
 250  */
 251 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 252 #define CFG_I2C_SLAVE           0x7F
 253
 254 /*
 255  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 256  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 257  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 258  * same configuration could be used.
 259  */
 260 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 261 #define CFG_I2C_EEPROM_ADDR_LEN         2
 262 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 263 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 264
 265 /*
 266  * HW-Monitor configuration on Mini-FAP
 267  */
 268 #if defined (CONFIG_MINIFAP)
 269 #define CFG_I2C_HWMON_ADDR              0x2C
 270 #endif
 271
 272 /* List of I2C addresses to be verified by POST */
 273 #if defined (CONFIG_MINIFAP)
 274 #undef I2C_ADDR_LIST
 275 #define I2C_ADDR_LIST   {       CFG_I2C_EEPROM_ADDR,    \
 276                                 CFG_I2C_HWMON_ADDR,     \
 277                                 CFG_I2C_SLAVE }
 278 #endif
 279
 280 /*
 281  * Flash configuration
 282  */
 283 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 284
 285 /* use CFI flash driver if no module variant is spezified */
 286 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 287 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 288 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 289 #define CFG_FLASH_EMPTY_INFO
 290 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 291 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 292 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 293
 294 #if !defined(CFG_LOWBOOT)
 295 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 296 #else   /* CFG_LOWBOOT */
 297 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 298 #endif  /* CFG_LOWBOOT */
 299 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 300                                            (= chip selects) */
 301 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 302 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 303
 304
 305 /*
 306  * Environment settings
 307  */
 308 #define CFG_ENV_IS_IN_FLASH     1
 309 #define CFG_ENV_SIZE            0x10000
 310 #define CFG_ENV_SECT_SIZE       0x20000
 311 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 312 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 313
 314 /*
 315  * Memory map
 316  */
 317 #define CFG_MBAR                0xF0000000
 318 #define CFG_SDRAM_BASE          0x00000000
 319 #define CFG_DEFAULT_MBAR        0x80000000
 320
 321 /* Use ON-Chip SRAM until RAM will be available */
 322 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 323 #ifdef CONFIG_POST
 324 /* preserve space for the post_word at end of on-chip SRAM */
 325 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 326 #else
 327 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 328 #endif
 329
 330
 331 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 332 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 333 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 334
 335 #define CFG_MONITOR_BASE        TEXT_BASE
 336 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 337 #   define CFG_RAMBOOT          1
 338 #endif
 339
 340 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 341 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 342 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 343
 344 /*
 345  * Ethernet configuration
 346  */
 347 #define CONFIG_MPC5xxx_FEC      1
 348 /*
 349  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 350  */
 351 /* #define CONFIG_FEC_10MBIT 1 */
 352 #define CONFIG_PHY_ADDR         0x00
 353
 354 /*
 355  * GPIO configuration
 356  *
 357  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 358  *      Bit 0 (mask: 0x80000000): 1
 359  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 360  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 361  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 362  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 363  *            (because, there I2C1 is used as I2C bus)
 364  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 365  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 366  *      000 -> All PSC2 pins are GIOPs
 367  *      001 -> CAN1/2 on PSC2 pins
 368  *             Use for REV100 STK52xx boards
 369  * use PSC6:
 370  *   on STK52xx:
 371  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 372  *      Bits 9:11 (mask: 0x00700000):
 373  *         101 -> PSC6 : Extended POST test is not available
 374  *   on MINI-FAP and TQM5200_IB:
 375  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 376  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 377  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 378  *   tests.
 379  */
 380 #if defined (CONFIG_MINIFAP)
 381 # define CFG_GPS_PORT_CONFIG    0x91000004
 382 #elif defined (CONFIG_STK52XX)
 383 # if defined (CONFIG_STK52XX_REV100)
 384 #  define CFG_GPS_PORT_CONFIG   0x81500014
 385 # else /* STK52xx REV200 and above */
 386 #  if defined (CONFIG_TQM5200_REV100)
 387 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 388 #  else/* TQM5200 REV200 and above */
 389 #   define CFG_GPS_PORT_CONFIG  0x91500004
 390 #  endif
 391 # endif
 392 #else  /* TMQ5200 Inbetriebnahme-Board */
 393 # define CFG_GPS_PORT_CONFIG    0x81000004
 394 #endif
 395
 396 /*
 397  * RTC configuration
 398  */
 399 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 400
 401 /*
 402  * Miscellaneous configurable options
 403  */
 404 #define CFG_LONGHELP                    /* undef to save memory     */
 405 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 406 #if defined(CONFIG_CMD_KGDB)
 407 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 408 #else
 409 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 410 #endif
 411 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 412 #define CFG_MAXARGS             16      /* max number of command args   */
 413 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 414
 415 /* Enable an alternate, more extensive memory test */
 416 #define CFG_ALT_MEMTEST
 417
 418 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 419 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 420
 421 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 422
 423 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 424
 425 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 426 #if defined(CONFIG_CMD_KGDB)
 427 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 428 #endif
 429
 430 /*
 431  * Enable loopw command.
 432  */
 433 #define CONFIG_LOOPW
 434
 435 /*
 436  * Various low-level settings
 437  */
 438 #if defined(CONFIG_MPC5200)
 439 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 440 #define CFG_HID0_FINAL          HID0_ICE
 441 #else
 442 #define CFG_HID0_INIT           0
 443 #define CFG_HID0_FINAL          0
 444 #endif
 445
 446 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 447 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 448 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 449 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 450 #else
 451 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 452 #endif
 453 #define CFG_CS0_START           CFG_FLASH_BASE
 454 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 455
 456 #define CONFIG_LAST_STAGE_INIT
 457
 458 /*
 459  * SRAM - Do not map below 2 GB in address space, because this area is used
 460  * for SDRAM autosizing.
 461  */
 462 #define CFG_CS2_START           0xE5000000
 463 #define CFG_CS2_SIZE            0x100000        /* 1 MByte */
 464 #define CFG_CS2_CFG             0x0004D930
 465
 466 /*
 467  * Grafic controller - Do not map below 2 GB in address space, because this
 468  * area is used for SDRAM autosizing.
 469  */
 470 #define SM501_FB_BASE           0xE0000000
 471 #define CFG_CS1_START           (SM501_FB_BASE)
 472 #define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
 473 #define CFG_CS1_CFG             0x8F48FF70
 474 #define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
 475
 476 #define CFG_CS_BURST            0x00000000
 477 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 478
 479 #define CFG_RESET_ADDRESS       0xff000000
 480
 481 /*-----------------------------------------------------------------------
 482  * USB stuff
 483  *-----------------------------------------------------------------------
 484  */
 485 #define CONFIG_USB_CLOCK        0x0001BBBB
 486 #define CONFIG_USB_CONFIG       0x00001000
 487
 488 /*-----------------------------------------------------------------------
 489  * IDE/ATA stuff Supports IDE harddisk
 490  *-----------------------------------------------------------------------
 491  */
 492
 493 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 494
 495 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 496 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 497
 498 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 499 #define CONFIG_IDE_PREINIT
 500
 501 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 502 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 503
 504 #define CFG_ATA_IDE0_OFFSET     0x0000
 505
 506 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 507
 508 /* Offset for data I/O                  */
 509 #define CFG_ATA_DATA_OFFSET     (0x0060)
 510
 511 /* Offset for normal register accesses  */
 512 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 513
 514 /* Offset for alternate registers       */
 515 #define CFG_ATA_ALT_OFFSET      (0x005C)
 516
 517 /* Interval between registers                                                */
 518 #define CFG_ATA_STRIDE          4
 519
 520 #endif /* __CONFIG_H */