include/configs/pmdra.h

   1 /*
   2  * Copyright (C) 2008 Prodrive BV <pieter.voorthijsen@prodrive.nl>
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24 #include <asm/sizes.h>
  25
  26 /*=======*/
  27 /* Board */
  28 /*=======*/
  29 #define CFG_PMDRA
  30 #define CFG_NAND_LARGEPAGE
  31 /*===================*/
  32 /* SoC Configuration */
  33 /*===================*/
  34 #define CONFIG_ARM926EJS                        /* arm926ejs CPU core */
  35 #define CONFIG_SYS_CLK_FREQ     ((CFG_HZ_CLOCK * (CFG_DAVINCI_PLL1_PLLM + 1))/2)
  36 #define CFG_TIMERBASE           0x01c21400      /* use timer 0 */
  37 #define CFG_HZ_CLOCK            27000000        /* Timer Input clock freq */
  38 #define CFG_HZ                  1000
  39 #define CFG_DAVINCI_PINMUX_0    0x00000c1f
  40 #define CFG_DAVINCI_WAITCFG     0x10000000
  41 #define CFG_DAVINCI_ACFG2       0x00460385      /* NOR CE Config */
  42 #define CFG_DAVINCI_ACFG3       0x0822218c      /* NAND CE Config */
  43 #define CFG_DAVINCI_ACFG4       0x3ffffffd
  44 #define CFG_DAVINCI_ACFG5       0x3ffffffd
  45 #define CFG_DAVINCI_NANDCE      3               /* Use CE3 for NAND */
  46 #define CFG_DAVINCI_DDRCTL      0x50006405      /* DDR timing config */
  47 #define CFG_DAVINCI_SDREF       0x000005c3
  48 #define CFG_DAVINCI_SDCFG       0x00178832      /* 8 banks , CAS = 4*/
  49 #define CFG_DAVINCI_SDTIM0      0x28923211
  50 #define CFG_DAVINCI_SDTIM1      0x0016c722
  51 #define CFG_DAVINCI_MMARG_BRF0  0x00444400
  52 /* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
  53 #define CFG_DAVINCI_PLL1_PLLM   0x12
  54 #define CFG_DAVINCI_PLL2_PLLM   0x17            /* 162 MHz */
  55 #define CFG_DAVINCI_PLL2_DIV1   0x0b            /* 54 MHz */
  56 #define CFG_DAVINCI_PLL2_DIV2   0x01
  57 /*====================================================*/
  58 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
  59 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
  60 /*====================================================*/
  61 #define CFG_I2C_EEPROM_ADDR_LEN         2
  62 #define CFG_I2C_EEPROM_ADDR             0x50
  63 #define CFG_EEPROM_PAGE_WRITE_BITS      6
  64 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
  65 /*=============*/
  66 /* Memory Info */
  67 /*=============*/
  68 #define CFG_MALLOC_LEN          (0x10000 + 128*1024)    /* malloc() len */
  69 #define CFG_GBL_DATA_SIZE       128             /* reserved for initial data */
  70 #define CFG_MEMTEST_START       0x80000000      /* memtest start address */
  71 #define CFG_MEMTEST_END         0x81000000      /* 16MB RAM test */
  72 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
  73 #define CONFIG_STACKSIZE        (256*1024)      /* regular stack */
  74 #define PHYS_SDRAM_1            0x80000000      /* DDR Start */
  75 #define PHYS_SDRAM_1_SIZE       0x10000000      /* DDR size 256MB */
  76 #define DDR_8BANKS                              /* 8-bank DDR2 (256MB) */
  77 /*====================*/
  78 /* Serial Driver info */
  79 /*====================*/
  80 #define CFG_NS16550
  81 #define CFG_NS16550_SERIAL
  82 #define CFG_NS16550_REG_SIZE    4               /* NS16550 register size */
  83 #define CFG_NS16550_COM1        0x01c20000      /* Base address of UART0 */
  84 #define CFG_NS16550_COM2        0x01c20800      /* Base address of UART2 */
  85 #define CFG_NS16550_CLK         27000000        /* Input clock to NS16550 */
  86 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
  87 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
  88 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  89 /*===================*/
  90 /* I2C Configuration */
  91 /*===================*/
  92 #define CONFIG_HARD_I2C
  93 #define CONFIG_DRIVER_DAVINCI_I2C
  94 #define CFG_I2C_SPEED           50000   /* 100Kbps won't work, silicon bug */
  95 #define CFG_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
  96 /*==================================*/
  97 /* Network & Ethernet Configuration */
  98 /*==================================*/
  99 #define CONFIG_DRIVER_TI_EMAC
 100 #define CONFIG_MII
 101 #define CONFIG_BOOTP_DEFAULT
 102 #define CONFIG_BOOTP_DNS
 103 #define CONFIG_BOOTP_DNS2
 104 #define CONFIG_BOOTP_SEND_HOSTNAME
 105 #define CONFIG_NET_RETRY_COUNT  10
 106 /*=====================*/
 107 /* Flash & Environment */
 108 /*=====================*/
 109 #define CFG_USE_NAND
 110 #define CFG_NAND_BASE           0x04000000
 111 #undef CFG_NAND_HW_ECC
 112 #define CFG_MAX_NAND_DEVICE     1               /* Max number of NAND devices */
 113 #define NAND_MAX_CHIPS          1
 114 #define DEF_BOOTM               ""
 115 #define CFG_ENV_IS_IN_FLASH     1
 116 #define CFG_FLASH_CFI_DRIVER
 117 #define CFG_FLASH_CFI
 118 #define CFG_MAX_FLASH_BANKS     1               /* max number of flash banks */
 119 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x40000)
 120 #define CFG_ENV_OFFSET          (CFG_ENV_ADDR)
 121 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)*/
 122 #define PHYS_FLASH_1            0x02000000      /* CS2 Base address */
 123 #define CFG_FLASH_BASE          PHYS_FLASH_1    /* Flash Base for U-Boot */
 124 #define PHYS_FLASH_SIZE         0x2000000       /* Flash size 32MB */
 125 #define CFG_MAX_FLASH_SECT      (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
 126 #define CFG_ENV_SECT_SIZE       CFG_FLASH_SECT_SZ       /* Env sector Size */
 127 #define CFG_FLASH_SECT_SZ       0x20000 /* 128KB sect size INTEL Flash */
 128 #define CFG_FLASH_PROTECTION    1
 129 /*==============================*/
 130 /* U-Boot general configuration */
 131 /*==============================*/
 132 #undef CONFIG_USE_IRQ                           /* No IRQ/FIQ in U-Boot */
 133 #define CONFIG_MISC_INIT_R
 134 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
 135 #define CFG_PROMPT              "U-Boot > "     /* Monitor Command Prompt */
 136 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size  */
 137 #define CFG_PBSIZE      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
 138 #define CFG_MAXARGS     16              /* max number of command args */
 139 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 140 #define CFG_LOAD_ADDR   0x80700000 /* default Linux kernel load address */
 141 #define CONFIG_VERSION_VARIABLE
 142 #define CONFIG_AUTO_COMPLETE    /* Won't work with hush so far, may be later */
 143 #define CFG_HUSH_PARSER
 144 #define CFG_PROMPT_HUSH_PS2     "> "
 145 #define CONFIG_CMDLINE_EDITING
 146 #define CFG_LONGHELP
 147 #define CONFIG_CRC32_VERIFY
 148 #define CONFIG_MX_CYCLIC
 149 #define CONFIG_ENV_OVERWRITE
 150 /*===================*/
 151 /* Linux Information */
 152 /*===================*/
 153 #define LINUX_BOOT_PARAM_ADDR   0x80000100
 154 #define CONFIG_CMDLINE_TAG
 155 #define CONFIG_SETUP_MEMORY_TAGS
 156 #define CONFIG_BOOTDELAY        2
 157 #define CONFIG_BOOTARGS \
 158         "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
 159 #define CONFIG_BOOTCOMMAND      "run nand"
 160 #define CONFIG_EXTRA_ENV_SETTINGS "ethaddr=00:11:22:33:44:55\n"
 161 /*=================*/
 162 /* U-Boot commands */
 163 /*=================*/
 164 #include <config_cmd_default.h>
 165 #define CONFIG_CMD_ASKENV
 166 #define CONFIG_CMD_DHCP
 167 #define CONFIG_CMD_DIAG
 168 #define CONFIG_CMD_I2C
 169 #define CONFIG_CMD_MII
 170 #define CONFIG_CMD_PING
 171 #define CONFIG_CMD_SAVES
 172 #define CONFIG_CMD_EEPROM
 173 #undef CONFIG_CMD_BDI
 174 #undef CONFIG_CMD_FPGA
 175 #undef CONFIG_CMD_SETGETDCR
 176 #define CONFIG_CMD_FLASH
 177 #undef CONFIG_CMD_IMLS
 178 #define CONFIG_CMD_NAND
 179 /*=======================*/
 180 /* KGDB support (if any) */
 181 /*=======================*/
 182 #ifdef CONFIG_CMD_KGDB
 183 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port */
 184 #define CONFIG_KGDB_SER_INDEX   1       /* which serial port to use */
 185 #endif
 186 #endif /* __CONFIG_H */