include/configs/hxd8.h

   1 /*
   2  * (C) Copyright 2007 OpenMoko, Inc.
   3  * Author: Harald Welte <laforge@openmoko.org>
   4  *
   5  * Configuation settings for the FIC HXD8
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /* we want to be able to start u-boot directly from within NAND flash */
  30 #define CONFIG_LL_INIT_NAND_ONLY
  31 #define CONFIG_S3C2410_NAND_BOOT        1
  32 #define CONFIG_S3C2410_NAND_SKIP_BAD    1
  33
  34 #define CFG_UBOOT_SIZE          0x40000 /* size of u-boot, for NAND loading */
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  41 #define CONFIG_S3C2440          1       /* in a SAMSUNG S3C2440 SoC     */
  42 #define CONFIG_SMDK2440         1       /* on a SAMSUNG SMDK2440 Board  */
  43 #define CONFIG_HXD8             1       /* on a FIC HXD8 Board  */
  44
  45 /* input clock of PLL */
  46 #define CONFIG_SYS_CLK_FREQ     16934400/* the HXD8 has this input clock */
  47
  48
  49 #define USE_920T_MMU            1
  50 #define CONFIG_USE_IRQ          1
  51
  52 /*
  53  * Size of malloc() pool
  54  */
  55 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 2048*1024)
  56                                         /* >> CFG_VIDEO_LOGO_MAX_SIZE */
  57 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  58
  59 /*
  60  * Hardware drivers
  61  */
  62
  63 /*
  64  * select serial console configuration
  65  */
  66 #define CONFIG_SERIAL3          1       /* we use SERIAL 3 on HXD8 */
  67
  68 /************************************************************
  69  * RTC
  70  ************************************************************/
  71 #define CONFIG_RTC_S3C24X0      1
  72
  73 /* allow to overwrite serial and ethaddr */
  74 #define CONFIG_ENV_OVERWRITE
  75
  76 #define CONFIG_BAUDRATE         115200
  77
  78 /***********************************************************
  79  * Command definition
  80  ***********************************************************/
  81
  82 #define CONFIG_CMD_BDI
  83 #define CONFIG_CMD_LOADS
  84 #define CONFIG_CMD_LOADB
  85 #define CONFIG_CMD_IMI
  86 #define CONFIG_CMD_CACHE
  87 #define CONFIG_CMD_MEMORY
  88 #define CONFIG_CMD_ENV
  89                         /* CFG_CMD_IRQ   | */
  90 #define CONFIG_CMD_BOOTD
  91 #define CONFIG_CMD_CONSOLE
  92                         /* CFG_CMD_BMP   | */
  93 #define CONFIG_CMD_ASKENV
  94 #define CONFIG_CMD_RUN
  95 #define CONFIG_CMD_ECHO
  96 #define CONFIG_CMD_I2C
  97 #define CONFIG_CMD_REGINFO
  98 #define CONFIG_CMD_IMMAP
  99 #define CONFIG_CMD_DATE
 100 #define CONFIG_CMD_AUTOSCRIPT
 101 #define CONFIG_CMD_BSP
 102 #define CONFIG_CMD_ELF
 103 #define CONFIG_CMD_MISC
 104                         /* CFG_CMD_USB   | */
 105 #define CONFIG_CMD_JFFS2
 106 #define CONFIG_CMD_DIAG
 107                         /* CFG_CMD_HWFLOW | */
 108 #define CONFIG_CMD_SAVES
 109 #define CONFIG_CMD_NAND
 110 #define CONFIG_CMD_PORTIO
 111 #define CONFIG_CMD_MMC
 112 #define CONFIG_CMD_FAT
 113 #define CONFIG_CMD_EXT2
 114 #define CONFIG_CMD_LICENSE
 115
 116 #define CONFIG_BOOTDELAY        3
 117 #define CONFIG_BOOTARGS         ""
 118 #define CONFIG_BOOTCOMMAND      "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
 119
 120 #define CONFIG_DOS_PARTITION    1
 121
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 124 /* what's this ? it's not used anywhere */
 125 #define CONFIG_KGDB_SER_INDEX   3               /* which serial port to use */
 126 #endif
 127
 128 /*
 129  * Miscellaneous configurable options
 130  */
 131 #define CFG_LONGHELP                            /* undef to save memory         */
 132 #define CFG_PROMPT              "HXD8 # "       /* Monitor Command Prompt       */
 133 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 134 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 135 #define CFG_MAXARGS             64              /* max number of command args   */
 136 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 137
 138 #define CFG_MEMTEST_START       0x30000000      /* memtest works on     */
 139 #define CFG_MEMTEST_END         0x33F00000      /* 63 MB in DRAM        */
 140
 141 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 142
 143 #define CFG_LOAD_ADDR           0x33000000      /* default load address */
 144
 145 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
 146 /* it to wrap 100 times (total 1562500) to get 1 sec. */
 147 #define CFG_HZ                  1562500
 148
 149 /* valid baudrates */
 150 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 151
 152 /*-----------------------------------------------------------------------
 153  * Stack sizes
 154  *
 155  * The stack sizes are set up in start.S using the settings below
 156  */
 157 #define CONFIG_STACKSIZE        (512*1024)      /* regular stack */
 158 #ifdef CONFIG_USE_IRQ
 159 #define CONFIG_STACKSIZE_IRQ    (8*1024)        /* IRQ stack */
 160 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 161 #endif
 162
 163 #if 0
 164 #define CONFIG_USB_OHCI_NEW     1
 165 #define CFG_USB_OHCI_CPU_INIT   1
 166 #define CFG_USB_OHCI_REGS_BASE  0x49000000 /* S3C24X0_USB_HOST_BASE */
 167 #define CFG_USB_OHCI_SLOT_NAME  "s3c2440"
 168 #define CFG_USB_OHCI_MAX_ROOT_PORTS     2
 169 #endif
 170
 171 #if 1
 172 #define CONFIG_USB_DEVICE       1
 173 #define CONFIG_USB_TTY          1
 174 #define CFG_CONSOLE_IS_IN_ENV   1
 175 #define CONFIG_USBD_VENDORID            0x1457     /* Linux/NetChip */
 176 #define CONFIG_USBD_PRODUCTID_GSERIAL   0x5120    /* gserial */
 177 #define CONFIG_USBD_PRODUCTID_CDCACM    0x511a    /* CDC ACM */
 178 #define CONFIG_USBD_MANUFACTURER        "OpenMoko, Inc"
 179 #define CONFIG_USBD_PRODUCT_NAME        "HXD8 Bootloader " U_BOOT_VERSION
 180 #define CONFIG_USBD_DFU                 1
 181 #define CONFIG_USBD_DFU_XFER_SIZE       4096    /* 0x4000 */
 182 #define CONFIG_USBD_DFU_INTERFACE       2
 183 #endif
 184 #define CFG_CONSOLE_IS_IN_ENV   1
 185
 186 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 187         "usbtty=cdc_acm\0"                                              \
 188         "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC2,115200 console=tty0 loglevel=8\0" \
 189         ""
 190
 191 /*-----------------------------------------------------------------------
 192  * Physical Memory Map
 193  */
 194 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 195 #define PHYS_SDRAM_1            0x30000000 /* SDRAM Bank #1 */
 196 #define PHYS_SDRAM_1_SIZE       0x08000000 /* 128 MB */
 197 #define PHYS_SDRAM_RES_SIZE     0x00200000 /* 2 MB for frame buffer */
 198
 199 /*-----------------------------------------------------------------------
 200  * FLASH and environment organization
 201  */
 202
 203 /* No NOR flash in this device */
 204 #define CFG_NO_FLASH            1
 205
 206 #define CFG_ENV_SIZE            0x20000         /* 128k Total Size of Environment Sector */
 207 #define CFG_ENV_IS_IN_NAND      1
 208 #define CFG_ENV_OFFSET_OOB      1               /* Location of ENV stored in block 0 OOB */
 209 #define CFG_PREBOOT_OVERRIDE    1       /* allow preboot from memory */
 210
 211 #define NAND_MAX_CHIPS          3
 212 #define CFG_NAND_BASE           0x4e000000
 213 #define CFG_MAX_NAND_DEVICE     NAND_MAX_CHIPS
 214 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE, CFG_NAND_BASE, CFG_NAND_BASE }
 215
 216 #define CONFIG_MMC              1
 217 #define CFG_MMC_BASE            0xff000000
 218
 219 /* EXT2 driver */
 220 #define CONFIG_EXT2             1
 221
 222 #define CONFIG_FAT              1
 223 #define CONFIG_SUPPORT_VFAT
 224
 225 #if 1
 226 /* JFFS2 driver */
 227 #define CONFIG_JFFS2_CMDLINE    1
 228 #define CONFIG_JFFS2_NAND       1
 229 #define CONFIG_JFFS2_NAND_DEV   0
 230 //#define CONFIG_JFFS2_NAND_OFF 0x634000
 231 //#define CONFIG_JFFS2_NAND_SIZE        0x39cc000
 232 #endif
 233
 234 /* ATAG configuration */
 235 #define CONFIG_INITRD_TAG               1
 236 #define CONFIG_SETUP_MEMORY_TAGS        1
 237 #define CONFIG_CMDLINE_TAG              1
 238 #define CONFIG_REVISION_TAG             1
 239 #if 0
 240 #define CONFIG_SERIAL_TAG               1
 241 #endif
 242
 243 #define CONFIG_DRIVER_S3C24X0_I2C       1
 244 #define CONFIG_HARD_I2C                 1
 245 #define CFG_I2C_SPEED                   400000  /* 400kHz according to PCF50606 data sheet */
 246 #define CFG_I2C_SLAVE                   0x7f
 247
 248 /* we have a board_late_init() function */
 249 #define BOARD_LATE_INIT                 1
 250
 251 #if 1
 252 #define CONFIG_VIDEO
 253 #define CONFIG_VIDEO_S3C2410
 254 #define CONFIG_CFB_CONSOLE
 255 #define CONFIG_VIDEO_LOGO
 256 #define CONFIG_SPLASH_SCREEN
 257 #define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
 258 #define CONFIG_VIDEO_BMP_GZIP
 259 #define CONFIG_VGA_AS_SINGLE_DEVICE
 260 #define CONFIG_CMD_UNZIP
 261
 262 #define VIDEO_KBD_INIT_FCT      0
 263 #define VIDEO_TSTC_FCT          serial_tstc
 264 #define VIDEO_GETC_FCT          serial_getc
 265
 266 #define LCD_VIDEO_ADDR          0x33d00000
 267 #endif
 268
 269 #define CONFIG_S3C2410_NAND_BBT                1
 270 //#define CONFIG_S3C2410_NAND_HWECC              1
 271
 272 #define CONFIG_DRIVER_PCF50606          1
 273
 274 #define MTDIDS_DEFAULT  "nand0=hxd8-nand"
 275 #define MTPARTS_DEFAULT "hxd8-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),0x3fd00000(jffs2)"
 276 #define CFG_NAND_DYNPART_MTD_KERNEL_NAME "hxd8-nand"
 277 #define CONFIG_NAND_DYNPART
 278
 279 #endif  /* __CONFIG_H */