include/configs/debris.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /* Environments */
  34
  35 /* bootargs */
  36 #define CONFIG_BOOTARGS \
  37         "console=ttyS0,9600 init=/linuxrc " \
  38         "root=/dev/nfs rw nfsroot=192.168.0.1:" \
  39         "/tftpboot/target " \
  40         "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
  41         "255.255.255.0:debris:eth0:none " \
  42         "mtdparts=phys:12m(root),-(kernel)"
  43
  44 /* bootcmd */
  45 #define CONFIG_BOOTCOMMAND \
  46         "tftp 800000 pImage; " \
  47         "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
  48         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  49         "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  50         "${netmask}:${hostname}:eth0:none " \
  51         "mtdparts=phys:12m(root),-(kernel); " \
  52         "bootm 800000"
  53
  54 /* bootdelay */
  55 #define CONFIG_BOOTDELAY        5       /* autoboot 5s */
  56
  57 /* baudrate */
  58 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  59
  60 /* loads_echo */
  61 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  62
  63 /* ethaddr */
  64 #undef CONFIG_ETHADDR
  65
  66 /* eth2addr */
  67 #undef CONFIG_ETH2ADDR
  68
  69 /* eth3addr */
  70 #undef CONFIG_ETH3ADDR
  71
  72 /* ipaddr */
  73 #define CONFIG_IPADDR   192.168.0.2
  74
  75 /* serverip */
  76 #define CONFIG_SERVERIP 192.168.0.1
  77
  78 /* autoload */
  79 #undef CFG_AUTOLOAD
  80
  81 /* rootpath */
  82 #define CONFIG_ROOTPATH /tftpboot/target
  83
  84 /* gatewayip */
  85 #define CONFIG_GATEWAYIP 192.168.0.1
  86
  87 /* netmask */
  88 #define CONFIG_NETMASK 255.255.255.0
  89
  90 /* hostname */
  91 #define CONFIG_HOSTNAME debris
  92
  93 /* bootfile */
  94 #define CONFIG_BOOTFILE pImage
  95
  96 /* loadaddr */
  97 #define CONFIG_LOADADDR 800000
  98
  99 /* preboot */
 100 #undef CONFIG_PREBOOT
 101
 102 /* clocks_in_mhz */
 103 #undef CONFIG_CLOCKS_IN_MHZ
 104
 105
 106 /*
 107  * High Level Configuration Options
 108  * (easy to change)
 109  */
 110
 111 #define CONFIG_MPC824X          1
 112 #define CONFIG_MPC8245          1
 113 #define CONFIG_DEBRIS           1
 114
 115 #if 0
 116 #define USE_DINK32              1
 117 #else
 118 #undef USE_DINK32
 119 #endif
 120
 121 #define CONFIG_CONS_INDEX       1
 122 #define CONFIG_BAUDRATE         9600
 123 #define CONFIG_DRAM_SPEED       100             /* MHz */
 124
 125
 126 /*
 127  * BOOTP options
 128  */
 129 #define CONFIG_BOOTP_BOOTFILESIZE
 130 #define CONFIG_BOOTP_BOOTPATH
 131 #define CONFIG_BOOTP_GATEWAY
 132 #define CONFIG_BOOTP_HOSTNAME
 133
 134
 135 /*
 136  * Command line configuration.
 137  */
 138 #include <config_cmd_default.h>
 139
 140 #define CONFIG_CMD_ASKENV
 141 #define CONFIG_CMD_CACHE
 142 #define CONFIG_CMD_DATE
 143 #define CONFIG_CMD_DHCP
 144 #define CONFIG_CMD_DIAG
 145 #define CONFIG_CMD_EEPROM
 146 #define CONFIG_CMD_ELF
 147 #define CONFIG_CMD_I2C
 148 #define CONFIG_CMD_JFFS2
 149 #define CONFIG_CMD_KGBD
 150 #define CONFIG_CMD_PCI
 151 #define CONFIG_CMD_PING
 152 #define CONFIG_CMD_SAVES
 153 #define CONFIG_CMD_SDRAM
 154
 155
 156 /*
 157  * Miscellaneous configurable options
 158  */
 159 #define CFG_LONGHELP            1               /* undef to save memory         */
 160 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 161 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 162 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size    */
 163 #define CFG_MAXARGS             16              /* max number of command args   */
 164 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 165 #define CFG_LOAD_ADDR           0x00100000      /* default load address         */
 166 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 167
 168 /*-----------------------------------------------------------------------
 169  * PCI stuff
 170  *-----------------------------------------------------------------------
 171  */
 172 #define CONFIG_PCI                              /* include pci support          */
 173 #define CONFIG_PCI_PNP
 174
 175 #define CONFIG_NET_MULTI                /* Multi ethernet cards support */
 176 #define CONFIG_EEPRO100
 177 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
 178 #define CONFIG_EEPRO100_SROM_WRITE
 179
 180 #define PCI_ENET0_IOADDR        0x80000000
 181 #define PCI_ENET0_MEMADDR       0x80000000
 182 #define PCI_ENET1_IOADDR        0x81000000
 183 #define PCI_ENET1_MEMADDR       0x81000000
 184 /*-----------------------------------------------------------------------
 185  * Start addresses for the final memory configuration
 186  * (Set up by the startup code)
 187  * Please note that CFG_SDRAM_BASE _must_ start at 0
 188  */
 189 #define CFG_SDRAM_BASE          0x00000000
 190 #define CFG_MAX_RAM_SIZE        0x20000000
 191 #define CONFIG_VERY_BIG_RAM
 192
 193 #define CFG_RESET_ADDRESS       0xFFF00100
 194
 195 #if defined (USE_DINK32)
 196 #define CFG_MONITOR_LEN         0x00040000
 197 #define CFG_MONITOR_BASE        0x00090000
 198 #define CFG_RAMBOOT             1
 199 #define CFG_INIT_RAM_ADDR       (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 200 #define CFG_INIT_RAM_END        0x10000
 201 #define CFG_GBL_DATA_SIZE       256  /* size in bytes reserved for initial data */
 202 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 203 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 204 #else
 205 #undef  CFG_RAMBOOT
 206 #define CFG_MONITOR_LEN         0x00040000
 207 #define CFG_MONITOR_BASE        TEXT_BASE
 208
 209 /*#define CFG_GBL_DATA_SIZE    256*/
 210 #define CFG_GBL_DATA_SIZE       128
 211
 212 #define CFG_INIT_RAM_ADDR     0x40000000
 213 #define CFG_INIT_RAM_END      0x1000
 214 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 215
 216 #endif
 217
 218 #define CFG_FLASH_BASE          0x7C000000
 219 #define CFG_FLASH_SIZE          (16*1024*1024)  /* debris has tiny eeprom       */
 220
 221 #define CFG_MALLOC_LEN          (512 << 10)     /* Reserve 512 kB for malloc()  */
 222
 223 #define CFG_MEMTEST_START       0x00000000      /* memtest works on             */
 224 #define CFG_MEMTEST_END         0x04000000      /* 0 ... 32 MB in DRAM          */
 225
 226 #define CFG_EUMB_ADDR           0xFC000000
 227
 228 #define CFG_FLASH_RANGE_BASE    0xFF000000      /* flash memory address range   */
 229 #define CFG_FLASH_RANGE_SIZE    0x01000000
 230 #define FLASH_BASE0_PRELIM      0x7C000000      /* debris flash         */
 231
 232 /*
 233  * JFFS2 partitions
 234  *
 235  */
 236 /* No command line, one static partition, whole device */
 237 #undef CONFIG_JFFS2_CMDLINE
 238 #define CONFIG_JFFS2_DEV                "nor0"
 239 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 240 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 241
 242 /* mtdparts command line support */
 243
 244 /* Use first bank for JFFS2, second bank contains U-Boot.
 245  *
 246  * Note: fake mtd_id's used, no linux mtd map file.
 247  */
 248 /*
 249 #define CONFIG_JFFS2_CMDLINE
 250 #define MTDIDS_DEFAULT          "nor0=debris-0"
 251 #define MTDPARTS_DEFAULT        "mtdparts=debris-0:-(jffs2)"
 252 */
 253
 254 #define CFG_ENV_IS_IN_NVRAM      1
 255 #define CONFIG_ENV_OVERWRITE     1
 256 #define CFG_NVRAM_ACCESS_ROUTINE 1
 257 #define CFG_ENV_ADDR            0xFF000000 /* right at the start of NVRAM  */
 258 #define CFG_ENV_SIZE            0x400   /* Size of the Environment - 8K    */
 259 #define CFG_ENV_OFFSET          0       /* starting right at the beginning */
 260
 261 #define CFG_NVRAM_BASE_ADDR     0xff000000
 262
 263 /*
 264  * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
 265  * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
 266  */
 267 #define CFG_NVRAM_VXWORKS_OFFS  0x6900
 268
 269 /*
 270  * select i2c support configuration
 271  *
 272  * Supported configurations are {none, software, hardware} drivers.
 273  * If the software driver is chosen, there are some additional
 274  * configuration items that the driver uses to drive the port pins.
 275  */
 276 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 277 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 278 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 279 #define CFG_I2C_SLAVE           0x7F
 280
 281 #ifdef CONFIG_SOFT_I2C
 282 #error "Soft I2C is not configured properly.  Please review!"
 283 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 284 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 285 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 286 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 287 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 288                                 else    iop->pdat &= ~0x00010000
 289 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 290                                 else    iop->pdat &= ~0x00020000
 291 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 292 #endif /* CONFIG_SOFT_I2C */
 293
 294 #define CFG_I2C_EEPROM_ADDR     0x57            /* EEPROM IS24C02               */
 295 #define CFG_I2C_EEPROM_ADDR_LEN 1               /* Bytes of address             */
 296 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 297 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 298
 299 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 300 #define CFG_FLASH_BANKS         { FLASH_BASE0_PRELIM }
 301
 302 /*-----------------------------------------------------------------------
 303  * Definitions for initial stack pointer and data area (in DPRAM)
 304  */
 305
 306 /*
 307  * NS16550 Configuration
 308  */
 309 #define CFG_NS16550
 310 #define CFG_NS16550_SERIAL
 311
 312 #define CFG_NS16550_REG_SIZE    1
 313
 314 #define CFG_NS16550_CLK         7372800
 315
 316 #define CFG_NS16550_COM1        0xFF080000
 317 #define CFG_NS16550_COM2        (CFG_NS16550_COM1 + 8)
 318 #define CFG_NS16550_COM3        (CFG_NS16550_COM1 + 16)
 319 #define CFG_NS16550_COM4        (CFG_NS16550_COM1 + 24)
 320
 321 /*
 322  * Low Level Configuration Settings
 323  * (address mappings, register initial values, etc.)
 324  * You should know what you are doing if you make changes here.
 325  */
 326
 327 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 328 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
 329
 330 #define CFG_DLL_EXTEND          0x00
 331 #define CFG_PCI_HOLD_DEL        0x20
 332
 333 #define CFG_ROMNAL      15      /* rom/flash next access time */
 334 #define CFG_ROMFAL      31      /* rom/flash access time */
 335
 336 #define CFG_REFINT      430     /* # of clocks between CBR refresh cycles */
 337
 338 #define CFG_DBUS_SIZE2  1       /* set for 8-bit RCS1, clear for 32,64 */
 339
 340 /* the following are for SDRAM only*/
 341 #define CFG_BSTOPRE     121     /* Burst To Precharge, sets open page interval */
 342 #define CFG_REFREC      8       /* Refresh to activate interval         */
 343 #define CFG_RDLAT       4       /* data latency from read command       */
 344 #define CFG_PRETOACT    3       /* Precharge to activate interval       */
 345 #define CFG_ACTTOPRE    5       /* Activate to Precharge interval       */
 346 #define CFG_ACTORW              3       /* Activate to R/W                      */
 347 #define CFG_SDMODE_CAS_LAT      3       /* SDMODE CAS latency                   */
 348 #define CFG_SDMODE_WRAP         0       /* SDMODE wrap type                     */
 349 #if 0
 350 #define CFG_SDMODE_BURSTLEN     2       /* OBSOLETE!  SDMODE Burst length 2=4, 3=8              */
 351 #endif
 352
 353 #define CFG_REGISTERD_TYPE_BUFFER   1
 354 #define CFG_EXTROM 1
 355 #define CFG_REGDIMM 0
 356
 357
 358 /* memory bank settings*/
 359 /*
 360  * only bits 20-29 are actually used from these vales to set the
 361  * start/end address the upper two bits will be 0, and the lower 20
 362  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 363  * end address
 364  */
 365 #define CFG_BANK0_START         0x00000000
 366 #define CFG_BANK0_END           (0x4000000 - 1)
 367 #define CFG_BANK0_ENABLE        1
 368 #define CFG_BANK1_START         0x04000000
 369 #define CFG_BANK1_END           (0x8000000 - 1)
 370 #define CFG_BANK1_ENABLE        1
 371 #define CFG_BANK2_START         0x3ff00000
 372 #define CFG_BANK2_END           0x3fffffff
 373 #define CFG_BANK2_ENABLE        0
 374 #define CFG_BANK3_START         0x3ff00000
 375 #define CFG_BANK3_END           0x3fffffff
 376 #define CFG_BANK3_ENABLE        0
 377 #define CFG_BANK4_START         0x00000000
 378 #define CFG_BANK4_END           0x00000000
 379 #define CFG_BANK4_ENABLE        0
 380 #define CFG_BANK5_START         0x00000000
 381 #define CFG_BANK5_END           0x00000000
 382 #define CFG_BANK5_ENABLE        0
 383 #define CFG_BANK6_START         0x00000000
 384 #define CFG_BANK6_END           0x00000000
 385 #define CFG_BANK6_ENABLE        0
 386 #define CFG_BANK7_START         0x00000000
 387 #define CFG_BANK7_END           0x00000000
 388 #define CFG_BANK7_ENABLE        0
 389 /*
 390  * Memory bank enable bitmask, specifying which of the banks defined above
 391  are actually present. MSB is for bank #7, LSB is for bank #0.
 392  */
 393 #define CFG_BANK_ENABLE         0x01
 394
 395 #define CFG_ODCR                0x75    /* configures line driver impedances,   */
 396                                         /* see 8240 book for bit definitions    */
 397 #define CFG_PGMAX               0x32    /* how long the 8240 retains the        */
 398                                         /* currently accessed page in memory    */
 399                                         /* see 8240 book for details            */
 400
 401 /* SDRAM 0 - 256MB */
 402 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 403 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 404
 405 /* stack in DCACHE @ 1GB (no backing mem) */
 406 #if defined(USE_DINK32)
 407 #define CFG_IBAT1L      (0x40000000 | BATL_PP_00 )
 408 #define CFG_IBAT1U      (0x40000000 | BATU_BL_128K )
 409 #else
 410 #define CFG_IBAT1L      (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 411 #define CFG_IBAT1U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 412 #endif
 413
 414 /* PCI memory */
 415 #define CFG_IBAT2L      (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 416 #define CFG_IBAT2U      (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 417
 418 /* Flash, config addrs, etc */
 419 #define CFG_IBAT3L      (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 420 #define CFG_IBAT3U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 421
 422 #define CFG_DBAT0L      CFG_IBAT0L
 423 #define CFG_DBAT0U      CFG_IBAT0U
 424 #define CFG_DBAT1L      CFG_IBAT1L
 425 #define CFG_DBAT1U      CFG_IBAT1U
 426 #define CFG_DBAT2L      CFG_IBAT2L
 427 #define CFG_DBAT2U      CFG_IBAT2U
 428 #define CFG_DBAT3L      CFG_IBAT3L
 429 #define CFG_DBAT3U      CFG_IBAT3U
 430
 431 /*
 432  * For booting Linux, the board info and command line data
 433  * have to be in the first 8 MB of memory, since this is
 434  * the maximum mapped by the Linux kernel during initialization.
 435  */
 436 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 437 /*-----------------------------------------------------------------------
 438  * FLASH organization
 439  */
 440 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 441 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 442
 443 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 444 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 445
 446 /*-----------------------------------------------------------------------
 447  * Cache Configuration
 448  */
 449 #define CFG_CACHELINE_SIZE      32      /* For MPC8240 CPU                      */
 450 #if defined(CONFIG_CMD_KGDB)
 451 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 452 #endif
 453
 454
 455 /*
 456  * Internal Definitions
 457  *
 458  * Boot Flags
 459  */
 460 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 461 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 462
 463
 464 /* values according to the manual */
 465
 466 #define CONFIG_DRAM_50MHZ       1
 467 #define CONFIG_SDRAM_50MHZ
 468
 469 #define CONFIG_DISK_SPINUP_TIME 1000000
 470
 471 #endif  /* __CONFIG_H */