include/configs/davinci_schmoogie.h

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22 #include <asm/sizes.h>
  23
  24 /*=======*/
  25 /* Board */
  26 /*=======*/
  27 #define SCHMOOGIE
  28 #define CFG_NAND_LARGEPAGE
  29 #define CFG_USE_NAND
  30 /*===================*/
  31 /* SoC Configuration */
  32 /*===================*/
  33 #define CONFIG_ARM926EJS                        /* arm926ejs CPU core */
  34 #define CONFIG_SYS_CLK_FREQ     297000000       /* Arm Clock frequency */
  35 #define CFG_TIMERBASE           0x01c21400      /* use timer 0 */
  36 #define CFG_HZ_CLOCK            27000000        /* Timer Input clock freq */
  37 #define CFG_HZ                  1000
  38 #define CFG_DAVINCI_PINMUX_0    0x00000c1f
  39 #define CFG_DAVINCI_WAITCFG     0x00000000
  40 #define CFG_DAVINCI_ACFG2       0x0432229c      /* CE configs */
  41 #define CFG_DAVINCI_ACFG3       0x3ffffffd
  42 #define CFG_DAVINCI_ACFG4       0x3ffffffd
  43 #define CFG_DAVINCI_ACFG5       0x3ffffffd
  44 #define CFG_DAVINCI_NANDCE      2       /* When using NAND, define 2,3 or 4 */
  45 #define CFG_DAVINCI_DDRCTL      0x50006405      /* DDR timing config */
  46 #define CFG_DAVINCI_SDREF       0x000005c3
  47 #define CFG_DAVINCI_SDCFG       0x00178622      /* 4 banks */
  48 #define CFG_DAVINCI_SDTIM0      0x28923211
  49 #define CFG_DAVINCI_SDTIM1      0x0016c722
  50 #define CFG_DAVINCI_MMARG_BRF0  0x00444400
  51 /* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
  52 #define CFG_DAVINCI_PLL1_PLLM   0x15
  53 #define CFG_DAVINCI_PLL2_PLLM   0x17            /* 162 MHz */
  54 #define CFG_DAVINCI_PLL2_DIV1   0x0b            /* 54 MHz */
  55 #define CFG_DAVINCI_PLL2_DIV2   0x01
  56 /*=============*/
  57 /* Memory Info */
  58 /*=============*/
  59 #define CFG_MALLOC_LEN          (0x10000 + 256*1024)    /* malloc() len */
  60 #define CFG_GBL_DATA_SIZE       128             /* reserved for initial data */
  61 #define CFG_MEMTEST_START       0x80000000      /* memtest start address */
  62 #define CFG_MEMTEST_END         0x81000000      /* 16MB RAM test */
  63 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
  64 #define CONFIG_STACKSIZE        (256*1024)      /* regular stack */
  65 #define PHYS_SDRAM_1            0x80000000      /* DDR Start */
  66 #define PHYS_SDRAM_1_SIZE       0x08000000      /* DDR size 128MB */
  67 /*====================*/
  68 /* Serial Driver info */
  69 /*====================*/
  70 #define CFG_NS16550
  71 #define CFG_NS16550_SERIAL
  72 #define CFG_NS16550_REG_SIZE    4               /* NS16550 register size */
  73 #define CFG_NS16550_COM1        0x01c20000      /* Base address of UART0 */
  74 #define CFG_NS16550_CLK         27000000        /* Input clock to NS16550 */
  75 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
  76 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
  77 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  78 /*===================*/
  79 /* I2C Configuration */
  80 /*===================*/
  81 #define CONFIG_HARD_I2C
  82 #define CONFIG_DRIVER_DAVINCI_I2C
  83 #define CFG_I2C_SPEED           80000   /* 100Kbps won't work, silicon bug */
  84 #define CFG_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
  85 /*==================================*/
  86 /* Network & Ethernet Configuration */
  87 /*==================================*/
  88 #define CONFIG_DRIVER_TI_EMAC
  89 #define CONFIG_MII
  90 #define CONFIG_BOOTP_DEFAULT
  91 #define CONFIG_BOOTP_DNS
  92 #define CONFIG_BOOTP_DNS2
  93 #define CONFIG_BOOTP_SEND_HOSTNAME
  94 #define CONFIG_NET_RETRY_COUNT  10
  95 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  96 /*=====================*/
  97 /* Flash & Environment */
  98 /*=====================*/
  99 #undef CFG_ENV_IS_IN_FLASH
 100 #define CFG_NO_FLASH
 101 #define CFG_ENV_IS_IN_NAND              /* U-Boot env in NAND Flash  */
 102 #define CFG_ENV_SECT_SIZE       2048    /* Env sector Size */
 103 #define CFG_ENV_SIZE            SZ_128K
 104 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is loaded by a bootloader */
 105 #define CONFIG_SKIP_RELOCATE_UBOOT      /* to a proper address, init done */
 106 #define CFG_NAND_BASE           0x02000000
 107 #define CFG_NAND_HW_ECC
 108 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices */
 109 #define NAND_MAX_CHIPS          1
 110 #define CFG_ENV_OFFSET          0x0     /* Block 0--not used by bootcode */
 111 /*=====================*/
 112 /* Board related stuff */
 113 /*=====================*/
 114 #define CONFIG_RTC_DS1307               /* RTC chip on SCHMOOGIE */
 115 #define CFG_I2C_RTC_ADDR        0x6f    /* RTC chip I2C address */
 116 #define CONFIG_HAS_UID
 117 #define CONFIG_UID_DS28CM00             /* Unique ID on SCHMOOGIE */
 118 #define CFG_UID_ADDR            0x50    /* UID chip I2C address */
 119 /*==============================*/
 120 /* U-Boot general configuration */
 121 /*==============================*/
 122 #undef  CONFIG_USE_IRQ                  /* No IRQ/FIQ in U-Boot */
 123 #define CONFIG_MISC_INIT_R
 124 #undef CONFIG_BOOTDELAY
 125 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
 126 #define CFG_PROMPT              "U-Boot > "     /* Monitor Command Prompt */
 127 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size  */
 128 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print buffer sz */
 129 #define CFG_MAXARGS             16              /* max number of command args */
 130 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 131 #define CFG_LOAD_ADDR           0x80700000      /* default Linux kernel load address */
 132 #define CONFIG_VERSION_VARIABLE
 133 #define CONFIG_AUTO_COMPLETE            /* Won't work with hush so far, may be later */
 134 #define CFG_HUSH_PARSER
 135 #define CFG_PROMPT_HUSH_PS2     "> "
 136 #define CONFIG_CMDLINE_EDITING
 137 #define CFG_LONGHELP
 138 #define CONFIG_CRC32_VERIFY
 139 #define CONFIG_MX_CYCLIC
 140 /*===================*/
 141 /* Linux Information */
 142 /*===================*/
 143 #define LINUX_BOOT_PARAM_ADDR   0x80000100
 144 #define CONFIG_CMDLINE_TAG
 145 #define CONFIG_SETUP_MEMORY_TAGS
 146 #define CONFIG_BOOTARGS         "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
 147 #define CONFIG_BOOTCOMMAND      "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
 148 /*=================*/
 149 /* U-Boot commands */
 150 /*=================*/
 151 #include <config_cmd_default.h>
 152 #define CONFIG_CMD_ASKENV
 153 #define CONFIG_CMD_DHCP
 154 #define CONFIG_CMD_DIAG
 155 #define CONFIG_CMD_I2C
 156 #define CONFIG_CMD_MII
 157 #define CONFIG_CMD_PING
 158 #define CONFIG_CMD_SAVES
 159 #define CONFIG_CMD_DATE
 160 #define CONFIG_CMD_NAND
 161 #undef CONFIG_CMD_EEPROM
 162 #undef CONFIG_CMD_BDI
 163 #undef CONFIG_CMD_FPGA
 164 #undef CONFIG_CMD_SETGETDCR
 165 #undef CONFIG_CMD_FLASH
 166 #undef CONFIG_CMD_IMLS
 167 /*=======================*/
 168 /* KGDB support (if any) */
 169 /*=======================*/
 170 #ifdef CONFIG_CMD_KGDB
 171 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port */
 172 #define CONFIG_KGDB_SER_INDEX   1       /* which serial port to use */
 173 #endif
 174 #endif /* __CONFIG_H */