include/configs/cmc_pu2.h

   1 /*
   2  * 2004-2005 Gary Jennejohn <garyj@denx.de>
   3  *
   4  * Configuration settings for the CMC PU2 board.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /* ARM asynchronous clock */
  29 #define AT91C_MAIN_CLOCK        179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
  30 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK/3)    /* peripheral clock */
  31
  32 #define AT91_SLOW_CLOCK         32768   /* slow clock */
  33
  34 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  35 #define CONFIG_AT91RM9200       1       /* It's an Atmel AT91RM9200 SoC */
  36 #define CONFIG_CMC_PU2          1       /* on an CMC_PU2 Board          */
  37 #undef  CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
  38 #define USE_920T_MMU            1
  39
  40 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  41 #define CONFIG_SETUP_MEMORY_TAGS 1
  42 #define CONFIG_INITRD_TAG       1
  43
  44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  45 #define CFG_USE_MAIN_OSCILLATOR         1
  46 /* flash */
  47 #define MC_PUIA_VAL     0x00000000
  48 #define MC_PUP_VAL      0x00000000
  49 #define MC_PUER_VAL     0x00000000
  50 #define MC_ASR_VAL      0x00000000
  51 #define MC_AASR_VAL     0x00000000
  52 #define EBI_CFGR_VAL    0x00000000
  53 #define SMC_CSR0_VAL    0x100032ad /* 16bit, 2 TDF, 4 WS */
  54
  55 /* clocks */
  56 #define PLLAR_VAL       0x2026BE04 /* 179,712 MHz for PCK */
  57 #define PLLBR_VAL       0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  58 #define MCKR_VAL        0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
  59
  60 /* sdram */
  61 #define PIOC_ASR_VAL    0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  62 #define PIOC_BSR_VAL    0x00000000
  63 #define PIOC_PDR_VAL    0xFFFF0000
  64 #define EBI_CSA_VAL     0x00000002 /* CS1=SDRAM */
  65 #define SDRC_CR_VAL     0x3399c1d4 /* set up the SDRAM */
  66 #define SDRAM           0x20000000 /* address of the SDRAM */
  67 #define SDRAM1          0x20000080 /* address of the SDRAM */
  68 #define SDRAM_VAL       0x00000000 /* value written to SDRAM */
  69 #define SDRC_MR_VAL     0x00000002 /* Precharge All */
  70 #define SDRC_MR_VAL1    0x00000004 /* refresh */
  71 #define SDRC_MR_VAL2    0x00000003 /* Load Mode Register */
  72 #define SDRC_MR_VAL3    0x00000000 /* Normal Mode */
  73 #define SDRC_TR_VAL     0x000002E0 /* Write refresh rate */
  74 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  75
  76 /*
  77  * Size of malloc() pool
  78  */
  79 #define CFG_MALLOC_LEN  (CFG_ENV_SIZE + 128*1024)
  80 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  81
  82 #define CONFIG_BAUDRATE         9600
  83
  84 /*
  85  * Hardware drivers
  86  */
  87
  88 /* define one of these to choose the DBGU, USART0  or USART1 as console */
  89 #undef CONFIG_DBGU
  90 #define CONFIG_USART0
  91 #undef CONFIG_USART1
  92
  93 #undef  CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
  94
  95 #undef  CONFIG_MODEM_SUPPORT            /* disable modem initialization stuff */
  96
  97 #define CONFIG_HARD_I2C
  98
  99 #ifdef CONFIG_HARD_I2C
 100 #define CFG_I2C_SPEED           0       /* not used */
 101 #define CFG_I2C_SLAVE           0       /* not used */
 102 #define CONFIG_RTC_RS5C372A             /* RICOH I2C RTC */
 103 #define CFG_I2C_RTC_ADDR        0x32
 104 #define CFG_I2C_EEPROM_ADDR     0x50
 105 #define CFG_I2C_EEPROM_ADDR_LEN 1
 106 #define CFG_I2C_EEPROM_ADDR_OVERFLOW
 107 #else
 108 #define CONFIG_TIMESTAMP
 109 #endif
 110 /* still about 20 kB free with this defined */
 111 #define CFG_LONGHELP
 112
 113 #define CONFIG_BOOTDELAY      1
 114
 115
 116 /*
 117  * BOOTP options
 118  */
 119 #define CONFIG_BOOTP_BOOTFILESIZE
 120 #define CONFIG_BOOTP_BOOTPATH
 121 #define CONFIG_BOOTP_GATEWAY
 122 #define CONFIG_BOOTP_HOSTNAME
 123
 124
 125 /*
 126  * Command line configuration.
 127  */
 128 #include <config_cmd_default.h>
 129
 130 #define CONFIG_CMD_DHCP
 131 #define CONFIG_CMD_NFS
 132 #define CONFIG_CMD_SNTP
 133
 134 #undef CONFIG_CMD_FPGA
 135 #undef CONFIG_CMD_MISC
 136
 137 #if defined(CONFIG_HARD_I2C)
 138     #define CONFIG_CMD_DATE
 139     #define CONFIG_CMD_EEPROM
 140     #define CONFIG_CMD_I2C
 141 #endif
 142
 143
 144 #define CFG_LONGHELP
 145
 146 #define AT91_SMART_MEDIA_ALE    (1 << 22)       /* our ALE is AD22 */
 147 #define AT91_SMART_MEDIA_CLE    (1 << 21)       /* our CLE is AD21 */
 148
 149 #define CONFIG_NR_DRAM_BANKS    1
 150 #define PHYS_SDRAM              0x20000000
 151 #define PHYS_SDRAM_SIZE         0x1000000       /* 16 megs */
 152
 153 #define CFG_MEMTEST_START       PHYS_SDRAM
 154 #define CFG_MEMTEST_END         CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 155
 156 #define CONFIG_DRIVER_ETHER
 157 #define CONFIG_NET_RETRY_COUNT          20
 158 #define CONFIG_AT91C_USE_RMII
 159
 160 #define CFG_SPI_WRITE_TOUT              (5*CFG_HZ)
 161 #define CFG_MAX_DATAFLASH_BANKS         2
 162 #define CFG_MAX_DATAFLASH_PAGES         16384
 163 #define CFG_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* Logical adress for CS0 */
 164 #define CFG_DATAFLASH_LOGIC_ADDR_CS3    0xD0000000      /* Logical adress for CS3 */
 165
 166 #define PHYS_FLASH_1                    0x10000000
 167 #define PHYS_FLASH_SIZE                 0x800000  /* 8 megs main flash */
 168 #define CFG_FLASH_BASE                  PHYS_FLASH_1
 169 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 170 #define CFG_MAX_FLASH_BANKS             1
 171 #define CFG_MAX_FLASH_SECT              256
 172 #define CFG_FLASH_ERASE_TOUT            (11 * CFG_HZ)   /* Timeout for Flash Erase */
 173 #define CFG_FLASH_WRITE_TOUT            ( 2 * CFG_HZ)   /* Timeout for Flash Write */
 174
 175 #define CFG_ENV_IS_IN_FLASH             1
 176 #define CFG_ENV_OFFSET                  0x20000         /* after u-boot.bin */
 177 #define CFG_ENV_SECT_SIZE               (64 << 10)      /* sectors are 64 kB */
 178 #define CFG_ENV_SIZE                    (16 << 10)      /* Use only 16 kB */
 179
 180 #define CFG_LOAD_ADDR           0x21000000  /* default load address */
 181
 182 #define CFG_BAUDRATE_TABLE      { 115200, 57600, 38400, 19200, 9600 }
 183
 184 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 185 #define CFG_CBSIZE              256             /* Console I/O Buffer Size */
 186 #define CFG_MAXARGS             32              /* max number of command args */
 187 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 188
 189 #define CFG_HZ 1000
 190 #define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)     /* AT91C_TC0_CMR is implicitly set to */
 191                                                 /* AT91C_TC_TIMER_DIV1_CLOCK */
 192
 193 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 194
 195 #ifdef CONFIG_USE_IRQ
 196 #error CONFIG_USE_IRQ not supported
 197 #endif
 198
 199 #define CONFIG_EXTRA_ENV_SETTINGS       \
 200         "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
 201                 "addmtd;bootm\0" \
 202         "nfsargs=setenv bootargs root=/dev/nfs rw " \
 203                 "nfsroot=${serverip}:${rootpath}\0" \
 204         "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
 205                 "addcons addmtd; bootm\0" \
 206         "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
 207         "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
 208         "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
 209                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
 210                 "${hostname}::off\0" \
 211         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 212         "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
 213                 "64k(environment),768k(linux),4096k(root),-\0" \
 214         "load=tftp ${loadaddr} ${loadfile}\0" \
 215         "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
 216                 "cp.b ${loadaddr} 10000000 ${filesize};" \
 217                 "protect on 10000000 1001ffff\0" \
 218         "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
 219                 "cp.b ${loadaddr} 10030000 ${filesize}\0" \
 220         "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
 221                 "cp.b ${loadaddr} 100f0000 ${filesize}\0" \
 222         "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
 223                 "cp.b ${loadaddr} 104f0000 ${filesize}\0" \
 224         "cramfsimage=cramfs_cmc-pu2.img\0" \
 225         "jffsimage=jffs2_cmc-pu2.img\0" \
 226         "loadfile=u-boot_cmc-pu2.bin\0" \
 227         "bootfile=uImage_cmc-pu2\0" \
 228         "loadaddr=0x20800000\0" \
 229         "hostname=CMC-TC-PU2\0" \
 230         "bootcmd=run dhcp_start;run flash_cramfs\0" \
 231         "autoload=n\0" \
 232         "dhcp_start=echo no DHCP\0" \
 233         "ipaddr=192.168.0.190\0"
 234 #endif  /* __CONFIG_H */