include/configs/TQM866M.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC866           1       /* This is a MPC866 CPU         */
  37 #define CONFIG_TQM866M          1       /* ...on a TQM8xxM module       */
  38
  39 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  40 #define CFG_8xx_CPUCLK_MIN              15000000        /*  15 MHz - CPU minimum clock  */
  41 #define CFG_8xx_CPUCLK_MAX              133000000       /* 133 MHz - CPU maximum clock  */
  42 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000        /*  50 MHz - CPU default clock  */
  43                                                 /* (it will be used if there is no      */
  44                                                 /* 'cpuclk' variable with valid value)  */
  45
  46 #undef CFG_MEASURE_CPUCLK                       /* Measure real cpu clock       */
  47                                                 /* (function measure_gclk()     */
  48                                                 /* will be called)              */
  49 #ifdef CFG_MEASURE_CPUCLK
  50 #define CFG_8XX_XIN             10000000        /* measure_gclk() needs this    */
  51 #endif
  52
  53 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  54
  55 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  56
  57 #define CONFIG_BOOTCOUNT_LIMIT
  58
  59 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  60
  61 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  62
  63 #define CONFIG_PREBOOT  "echo;" \
  64         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  65         "echo"
  66
  67 #undef  CONFIG_BOOTARGS
  68
  69 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  70         "netdev=eth0\0"                                                 \
  71         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  72                 "nfsroot=${serverip}:${rootpath}\0"                     \
  73         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  74         "addip=setenv bootargs ${bootargs} "                            \
  75                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  76                 ":${hostname}:${netdev}:off panic=1\0"                  \
  77         "flash_nfs=run nfsargs addip;"                                  \
  78                 "bootm ${kernel_addr}\0"                                \
  79         "flash_self=run ramargs addip;"                                 \
  80                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  81         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  82         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  83         "bootfile=/tftpboot/TQM866M/uImage\0"                           \
  84         "fdt_addr=400C0000\0"                                           \
  85         "kernel_addr=40100000\0"                                        \
  86         "ramdisk_addr=40280000\0"                                       \
  87         "load=tftp 200000 ${u-boot}\0"                                  \
  88         "update=protect off 40000000 +${filesize};"                     \
  89                 "erase 40000000 +${filesize};"                          \
  90                 "cp.b 200000 40000000 ${filesize};"                     \
  91                 "protect on 40000000 +${filesize}\0"                    \
  92         ""
  93 #define CONFIG_BOOTCOMMAND      "run flash_self"
  94
  95 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  96 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  97
  98 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  99
 100 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 101
 102 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 103
 104 /* enable I2C and select the hardware/software driver */
 105 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 106 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 107
 108 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 109 #define CFG_I2C_SLAVE           0xFE
 110
 111 #ifdef CONFIG_SOFT_I2C
 112 /*
 113  * Software (bit-bang) I2C driver configuration
 114  */
 115 #define PB_SCL          0x00000020      /* PB 26 */
 116 #define PB_SDA          0x00000010      /* PB 27 */
 117
 118 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 119 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 120 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 121 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 122 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 123                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 124 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 125                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 126 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 127 #endif  /* CONFIG_SOFT_I2C */
 128
 129 #define CFG_I2C_EEPROM_ADDR     0x50            /* EEPROM AT24C256      */
 130 #define CFG_I2C_EEPROM_ADDR_LEN 2               /* two byte address     */
 131 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 132 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 133
 134 /*
 135  * BOOTP options
 136  */
 137 #define CONFIG_BOOTP_SUBNETMASK
 138 #define CONFIG_BOOTP_GATEWAY
 139 #define CONFIG_BOOTP_HOSTNAME
 140 #define CONFIG_BOOTP_BOOTPATH
 141 #define CONFIG_BOOTP_BOOTFILESIZE
 142
 143
 144 #define CONFIG_MAC_PARTITION
 145 #define CONFIG_DOS_PARTITION
 146
 147 #undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 148
 149 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 150
 151
 152 /*
 153  * Command line configuration.
 154  */
 155 #include <config_cmd_default.h>
 156
 157 #define CONFIG_CMD_ASKENV
 158 #define CONFIG_CMD_DHCP
 159 #define CONFIG_CMD_EEPROM
 160 #define CONFIG_CMD_I2C
 161 #define CONFIG_CMD_IDE
 162 #define CONFIG_CMD_NFS
 163
 164
 165 /*
 166  * Miscellaneous configurable options
 167  */
 168 #define CFG_LONGHELP                    /* undef to save memory         */
 169 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 170
 171 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 172 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 173 #ifdef  CFG_HUSH_PARSER
 174 #define CFG_PROMPT_HUSH_PS2     "> "
 175 #endif
 176
 177 #if defined(CONFIG_CMD_KGDB)
 178 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 179 #else
 180 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 181 #endif
 182 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 183 #define CFG_MAXARGS             16      /* max number of command args   */
 184 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 185
 186 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 187 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 188
 189 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 190
 191 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 192
 193 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 194
 195 /*
 196  * Low Level Configuration Settings
 197  * (address mappings, register initial values, etc.)
 198  * You should know what you are doing if you make changes here.
 199  */
 200 /*-----------------------------------------------------------------------
 201  * Internal Memory Mapped Register
 202  */
 203 #define CFG_IMMR                0xFFF00000
 204
 205 /*-----------------------------------------------------------------------
 206  * Definitions for initial stack pointer and data area (in DPRAM)
 207  */
 208 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 209 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 210 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 211 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 212 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 213
 214 /*-----------------------------------------------------------------------
 215  * Start addresses for the final memory configuration
 216  * (Set up by the startup code)
 217  * Please note that CFG_SDRAM_BASE _must_ start at 0
 218  */
 219 #define CFG_SDRAM_BASE          0x00000000
 220 #define CFG_FLASH_BASE          0x40000000
 221 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 222 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 223 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc()  */
 224
 225 /*
 226  * For booting Linux, the board info and command line data
 227  * have to be in the first 8 MB of memory, since this is
 228  * the maximum mapped by the Linux kernel during initialization.
 229  */
 230 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 231
 232 /*-----------------------------------------------------------------------
 233  * FLASH organization
 234  */
 235 /* use CFI flash driver */
 236 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 237 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 238 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 239 #define CFG_FLASH_EMPTY_INFO
 240 #define CFG_FLASH_USE_BUFFER_WRITE      1
 241 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 242 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip */
 243
 244 #define CFG_ENV_IS_IN_FLASH     1
 245 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 246 #define CFG_ENV_SIZE            0x08000 /* Total Size of Environment Sector     */
 247 #define CFG_ENV_SECT_SIZE       0x40000 /* Total Size of Environment Sector     */
 248
 249 /* Address and size of Redundant Environment Sector     */
 250 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
 251 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 252
 253 #define CFG_USE_PPCENV                  /* Environment embedded in sect .ppcenv */
 254
 255 /*-----------------------------------------------------------------------
 256  * Hardware Information Block
 257  */
 258 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 259 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 260 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 261
 262 /*-----------------------------------------------------------------------
 263  * Cache Configuration
 264  */
 265 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 266 #if defined(CONFIG_CMD_KGDB)
 267 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 268 #endif
 269
 270 /*-----------------------------------------------------------------------
 271  * SYPCR - System Protection Control                            11-9
 272  * SYPCR can only be written once after reset!
 273  *-----------------------------------------------------------------------
 274  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 275  */
 276 #if defined(CONFIG_WATCHDOG)
 277 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 278                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 279 #else
 280 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 281 #endif
 282
 283 /*-----------------------------------------------------------------------
 284  * SIUMCR - SIU Module Configuration                            11-6
 285  *-----------------------------------------------------------------------
 286  * PCMCIA config., multi-function pin tri-state
 287  */
 288 #ifndef CONFIG_CAN_DRIVER
 289 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 290 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 291 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 292 #endif  /* CONFIG_CAN_DRIVER */
 293
 294 /*-----------------------------------------------------------------------
 295  * TBSCR - Time Base Status and Control                         11-26
 296  *-----------------------------------------------------------------------
 297  * Clear Reference Interrupt Status, Timebase freezing enabled
 298  */
 299 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 300
 301 /*-----------------------------------------------------------------------
 302  * PISCR - Periodic Interrupt Status and Control                11-31
 303  *-----------------------------------------------------------------------
 304  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 305  */
 306 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 307
 308 /*-----------------------------------------------------------------------
 309  * SCCR - System Clock and reset Control Register               15-27
 310  *-----------------------------------------------------------------------
 311  * Set clock output, timebase and RTC source and divider,
 312  * power management and some other internal clocks
 313  */
 314 #define SCCR_MASK       SCCR_EBDF11
 315 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 316                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 317                          SCCR_DFALCD00)
 318
 319 /*-----------------------------------------------------------------------
 320  * PCMCIA stuff
 321  *-----------------------------------------------------------------------
 322  *
 323  */
 324 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 325 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 326 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 327 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 328 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 329 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 330 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 331 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 332
 333 /*-----------------------------------------------------------------------
 334  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 335  *-----------------------------------------------------------------------
 336  */
 337
 338 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 339
 340 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 341 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 342 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 343
 344 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 345 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 346
 347 #define CFG_ATA_IDE0_OFFSET     0x0000
 348
 349 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 350
 351 /* Offset for data I/O                  */
 352 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 353
 354 /* Offset for normal register accesses  */
 355 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 356
 357 /* Offset for alternate registers       */
 358 #define CFG_ATA_ALT_OFFSET      0x0100
 359
 360 /*-----------------------------------------------------------------------
 361  *
 362  *-----------------------------------------------------------------------
 363  *
 364  */
 365 #define CFG_DER 0
 366
 367 /*
 368  * Init Memory Controller:
 369  *
 370  * BR0/1 and OR0/1 (FLASH)
 371  */
 372
 373 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 374 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 375
 376 /* used to re-map FLASH both when starting from SRAM or FLASH:
 377  * restrict access enough to keep SRAM working (if any)
 378  * but not too much to meddle with FLASH accesses
 379  */
 380 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 381 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 382
 383 /*
 384  * FLASH timing: Default value of OR0 after reset
 385  */
 386 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 387                                  OR_SCY_15_CLK | OR_TRLX)
 388
 389 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 390 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 391 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 392
 393 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 394 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 395 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 396
 397 /*
 398  * BR2/3 and OR2/3 (SDRAM)
 399  *
 400  */
 401 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 402 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 403 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 404
 405 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 406 #define CFG_OR_TIMING_SDRAM     0x00000A00
 407
 408 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 409 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 410
 411 #ifndef CONFIG_CAN_DRIVER
 412 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 413 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 414 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 415 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 416 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 417 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 418 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 419                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 420 #endif  /* CONFIG_CAN_DRIVER */
 421
 422 /*
 423  * 4096 Rows from SDRAM example configuration
 424  * 1000 factor s -> ms
 425  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 426  * 4    Number of refresh cycles per period
 427  * 64   Refresh cycle in ms per number of rows
 428  */
 429 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
 430
 431 /*
 432  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 433  *
 434  *                        CPUclock(MHz) * 31.2
 435  * CFG_MAMR_PTA = -----------------------------------     with DFBRG = 0
 436  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 437  *
 438  * CPU clock =  15 MHz:  CFG_MAMR_PTA =  29   ->  4 * 7.73 us
 439  * CPU clock =  50 MHz:  CFG_MAMR_PTA =  97   ->  4 * 7.76 us
 440  * CPU clock =  66 MHz:  CFG_MAMR_PTA = 128   ->  4 * 7.75 us
 441  * CPU clock = 133 MHz:  CFG_MAMR_PTA = 255   ->  4 * 7.67 us
 442  *
 443  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 444  * be met also in the default configuration, i.e. if environment variable
 445  * 'cpuclk' is not set.
 446  */
 447 #define CFG_MAMR_PTA            97
 448
 449 /*
 450  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 451  */
 452 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 453 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16
 454 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 455 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8
 456
 457 /*
 458  * MAMR settings for SDRAM
 459  */
 460
 461 /* 8 column SDRAM */
 462 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 463                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 464                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 465 /* 9 column SDRAM */
 466 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 467                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 468                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 469 /* 10 column SDRAM */
 470 #define CFG_MAMR_10COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 471                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 472                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 473
 474 /*
 475  * Internal Definitions
 476  *
 477  * Boot Flags
 478  */
 479 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 480 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 481
 482 #define CONFIG_SCC1_ENET
 483 #define CONFIG_FEC_ENET
 484 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 485
 486 #endif  /* __CONFIG_H */