Working nand, mtdparts and proper machine ID (1999)
[u-boot-openmoko/mini2440.git] / include / configs / TQM855M.h
blob2696ea502b00926291523ba6867aa1c0edbd3b95
1 /*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
25 * board/config.h - configuration options, board specific
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
32 * High Level Configuration Options
33 * (easy to change)
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45 #define CONFIG_BOOTCOUNT_LIMIT
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #define CONFIG_BOARD_TYPES 1 /* support board types */
51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
53 "echo"
55 #undef CONFIG_BOOTARGS
57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=${serverip}:${rootpath}\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \
66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "bootfile=/tftpboot/TQM855M/uImage\0" \
72 "fdt_addr=40080000\0" \
73 "kernel_addr=400A0000\0" \
74 "ramdisk_addr=40280000\0" \
76 #define CONFIG_BOOTCOMMAND "run flash_self"
78 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
81 #undef CONFIG_WATCHDOG /* watchdog disabled */
83 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
85 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
87 /* enable I2C and select the hardware/software driver */
88 #undef CONFIG_HARD_I2C /* I2C with hardware support */
89 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
91 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
92 #define CFG_I2C_SLAVE 0xFE
94 #ifdef CONFIG_SOFT_I2C
96 * Software (bit-bang) I2C driver configuration
98 #define PB_SCL 0x00000020 /* PB 26 */
99 #define PB_SDA 0x00000010 /* PB 27 */
101 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
102 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
103 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
104 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
105 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
106 else immr->im_cpm.cp_pbdat &= ~PB_SDA
107 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
108 else immr->im_cpm.cp_pbdat &= ~PB_SCL
109 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
110 #endif /* CONFIG_SOFT_I2C */
112 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
113 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
114 #if 0
115 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
116 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
117 #define CFG_EEPROM_PAGE_WRITE_BITS 5
118 #endif
121 * BOOTP options
123 #define CONFIG_BOOTP_SUBNETMASK
124 #define CONFIG_BOOTP_GATEWAY
125 #define CONFIG_BOOTP_HOSTNAME
126 #define CONFIG_BOOTP_BOOTPATH
127 #define CONFIG_BOOTP_BOOTFILESIZE
130 #define CONFIG_MAC_PARTITION
131 #define CONFIG_DOS_PARTITION
133 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
137 * Command line configuration.
139 #include <config_cmd_default.h>
141 #define CONFIG_CMD_ASKENV
142 #define CONFIG_CMD_DATE
143 #define CONFIG_CMD_DHCP
144 #define CONFIG_CMD_EEPROM
145 #define CONFIG_CMD_IDE
146 #define CONFIG_CMD_NFS
147 #define CONFIG_CMD_SNTP
151 * Miscellaneous configurable options
153 #define CFG_LONGHELP /* undef to save memory */
154 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
156 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
157 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
158 #ifdef CFG_HUSH_PARSER
159 #define CFG_PROMPT_HUSH_PS2 "> "
160 #endif
162 #if defined(CONFIG_CMD_KGDB)
163 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
164 #else
165 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
166 #endif
167 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
168 #define CFG_MAXARGS 16 /* max number of command args */
169 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
171 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
172 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
174 #define CFG_LOAD_ADDR 0x100000 /* default load address */
176 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
178 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
181 * Low Level Configuration Settings
182 * (address mappings, register initial values, etc.)
183 * You should know what you are doing if you make changes here.
185 /*-----------------------------------------------------------------------
186 * Internal Memory Mapped Register
188 #define CFG_IMMR 0xFFF00000
190 /*-----------------------------------------------------------------------
191 * Definitions for initial stack pointer and data area (in DPRAM)
193 #define CFG_INIT_RAM_ADDR CFG_IMMR
194 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
195 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
196 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
197 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
199 /*-----------------------------------------------------------------------
200 * Start addresses for the final memory configuration
201 * (Set up by the startup code)
202 * Please note that CFG_SDRAM_BASE _must_ start at 0
204 #define CFG_SDRAM_BASE 0x00000000
205 #define CFG_FLASH_BASE 0x40000000
206 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
207 #define CFG_MONITOR_BASE CFG_FLASH_BASE
208 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
211 * For booting Linux, the board info and command line data
212 * have to be in the first 8 MB of memory, since this is
213 * the maximum mapped by the Linux kernel during initialization.
215 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
217 /*-----------------------------------------------------------------------
218 * FLASH organization
221 /* use CFI flash driver */
222 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
223 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
224 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
225 #define CFG_FLASH_EMPTY_INFO
226 #define CFG_FLASH_USE_BUFFER_WRITE 1
227 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
228 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
230 #define CFG_ENV_IS_IN_FLASH 1
231 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
232 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
233 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
235 /* Address and size of Redundant Environment Sector */
236 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
237 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
239 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
241 /*-----------------------------------------------------------------------
242 * Hardware Information Block
244 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
245 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
246 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
248 /*-----------------------------------------------------------------------
249 * Cache Configuration
251 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
252 #if defined(CONFIG_CMD_KGDB)
253 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
254 #endif
256 /*-----------------------------------------------------------------------
257 * SYPCR - System Protection Control 11-9
258 * SYPCR can only be written once after reset!
259 *-----------------------------------------------------------------------
260 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
262 #if defined(CONFIG_WATCHDOG)
263 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
265 #else
266 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
267 #endif
269 /*-----------------------------------------------------------------------
270 * SIUMCR - SIU Module Configuration 11-6
271 *-----------------------------------------------------------------------
272 * PCMCIA config., multi-function pin tri-state
274 #ifndef CONFIG_CAN_DRIVER
275 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
276 #else /* we must activate GPL5 in the SIUMCR for CAN */
277 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
278 #endif /* CONFIG_CAN_DRIVER */
280 /*-----------------------------------------------------------------------
281 * TBSCR - Time Base Status and Control 11-26
282 *-----------------------------------------------------------------------
283 * Clear Reference Interrupt Status, Timebase freezing enabled
285 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
287 /*-----------------------------------------------------------------------
288 * RTCSC - Real-Time Clock Status and Control Register 11-27
289 *-----------------------------------------------------------------------
291 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
293 /*-----------------------------------------------------------------------
294 * PISCR - Periodic Interrupt Status and Control 11-31
295 *-----------------------------------------------------------------------
296 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
298 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
300 /*-----------------------------------------------------------------------
301 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
302 *-----------------------------------------------------------------------
303 * Reset PLL lock status sticky bit, timer expired status bit and timer
304 * interrupt status bit
306 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
308 /*-----------------------------------------------------------------------
309 * SCCR - System Clock and reset Control Register 15-27
310 *-----------------------------------------------------------------------
311 * Set clock output, timebase and RTC source and divider,
312 * power management and some other internal clocks
314 #define SCCR_MASK SCCR_EBDF11
315 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
316 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
317 SCCR_DFALCD00)
319 /*-----------------------------------------------------------------------
320 * PCMCIA stuff
321 *-----------------------------------------------------------------------
324 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
325 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
326 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
327 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
328 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
329 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
330 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
331 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
333 /*-----------------------------------------------------------------------
334 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
335 *-----------------------------------------------------------------------
338 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
340 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
341 #undef CONFIG_IDE_LED /* LED for ide not supported */
342 #undef CONFIG_IDE_RESET /* reset for ide not supported */
344 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
345 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
347 #define CFG_ATA_IDE0_OFFSET 0x0000
349 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
351 /* Offset for data I/O */
352 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
354 /* Offset for normal register accesses */
355 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
357 /* Offset for alternate registers */
358 #define CFG_ATA_ALT_OFFSET 0x0100
360 /*-----------------------------------------------------------------------
362 *-----------------------------------------------------------------------
365 #define CFG_DER 0
368 * Init Memory Controller:
370 * BR0/1 and OR0/1 (FLASH)
373 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
374 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
376 /* used to re-map FLASH both when starting from SRAM or FLASH:
377 * restrict access enough to keep SRAM working (if any)
378 * but not too much to meddle with FLASH accesses
380 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
381 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
384 * FLASH timing:
386 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
387 OR_SCY_3_CLK | OR_EHTR | OR_BI)
389 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
390 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
391 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
393 #define CFG_OR1_REMAP CFG_OR0_REMAP
394 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
395 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
398 * BR2/3 and OR2/3 (SDRAM)
401 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
402 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
403 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
405 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
406 #define CFG_OR_TIMING_SDRAM 0x00000A00
408 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
409 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
411 #ifndef CONFIG_CAN_DRIVER
412 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
413 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
414 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
415 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
416 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
417 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
418 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
419 BR_PS_8 | BR_MS_UPMB | BR_V )
420 #endif /* CONFIG_CAN_DRIVER */
423 * Memory Periodic Timer Prescaler
425 * The Divider for PTA (refresh timer) configuration is based on an
426 * example SDRAM configuration (64 MBit, one bank). The adjustment to
427 * the number of chip selects (NCS) and the actually needed refresh
428 * rate is done by setting MPTPR.
430 * PTA is calculated from
431 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
433 * gclk CPU clock (not bus clock!)
434 * Trefresh Refresh cycle * 4 (four word bursts used)
436 * 4096 Rows from SDRAM example configuration
437 * 1000 factor s -> ms
438 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
439 * 4 Number of refresh cycles per period
440 * 64 Refresh cycle in ms per number of rows
441 * --------------------------------------------
442 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
444 * 50 MHz => 50.000.000 / Divider = 98
445 * 66 Mhz => 66.000.000 / Divider = 129
446 * 80 Mhz => 80.000.000 / Divider = 156
449 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
450 #define CFG_MAMR_PTA 98
453 * For 16 MBit, refresh rates could be 31.3 us
454 * (= 64 ms / 2K = 125 / quad bursts).
455 * For a simpler initialization, 15.6 us is used instead.
457 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
458 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
460 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
461 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
463 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
464 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
465 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
468 * MAMR settings for SDRAM
471 /* 8 column SDRAM */
472 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
473 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
475 /* 9 column SDRAM */
476 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
477 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
482 * Internal Definitions
484 * Boot Flags
486 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
487 #define BOOTFLAG_WARM 0x02 /* Software reboot */
489 #define CONFIG_SCC1_ENET
490 #define CONFIG_FEC_ENET
491 #define CONFIG_ETHPRIME "SCC ETHERNET"
493 #endif /* __CONFIG_H */