include/configs/TB5200.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2006
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #define CONFIG_TB5200           1       /* ... on a TB5200 base board */
  39
  40 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  41
  42 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  43 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48 #define CONFIG_PSC_CONSOLE      1       /* default console is on PSC1 */
  49 #define CONFIG_SERIAL_MULTI     1       /* support multiple consoles */
  50 #define CONFIG_PSC_CONSOLE2     6       /* second console is on PSC6 */
  51 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  52 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  53
  54 /*
  55  * Video console
  56  */
  57 #if 1
  58 #define CONFIG_VIDEO
  59 #define CONFIG_VIDEO_SM501
  60 #define CONFIG_VIDEO_SM501_32BPP
  61 #define CONFIG_CFB_CONSOLE
  62 #define CONFIG_VIDEO_LOGO
  63 #define CONFIG_VGA_AS_SINGLE_DEVICE
  64 #define CONFIG_CONSOLE_EXTRA_INFO
  65 #define CONFIG_VIDEO_SW_CURSOR
  66 #define CONFIG_SPLASH_SCREEN
  67 #define CFG_CONSOLE_IS_IN_ENV
  68 #endif
  69
  70 /* Partitions */
  71 #define CONFIG_MAC_PARTITION
  72 #define CONFIG_DOS_PARTITION
  73 #define CONFIG_ISO_PARTITION
  74
  75 /* USB */
  76 #define CONFIG_USB_OHCI
  77 #define CONFIG_USB_STORAGE
  78
  79 /* POST support */
  80 #define CONFIG_POST             (CFG_POST_MEMORY   | \
  81                                  CFG_POST_CPU      | \
  82                                  CFG_POST_I2C)
  83
  84 #ifdef CONFIG_POST
  85 /* preserve space for the post_word at end of on-chip SRAM */
  86 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  87 #endif
  88
  89
  90 /*
  91  * BOOTP options
  92  */
  93 #define CONFIG_BOOTP_BOOTFILESIZE
  94 #define CONFIG_BOOTP_BOOTPATH
  95 #define CONFIG_BOOTP_GATEWAY
  96 #define CONFIG_BOOTP_HOSTNAME
  97
  98
  99 /*
 100  * Command line configuration.
 101  */
 102 #include <config_cmd_default.h>
 103
 104 #define CONFIG_CMD_ASKENV
 105 #define CONFIG_CMD_DATE
 106 #define CONFIG_CMD_DHCP
 107 #define CONFIG_CMD_ECHO
 108 #define CONFIG_CMD_EEPROM
 109 #define CONFIG_CMD_EXT2
 110 #define CONFIG_CMD_FAT
 111 #define CONFIG_CMD_I2C
 112 #define CONFIG_CMD_IDE
 113 #define CONFIG_CMD_JFFS2
 114 #define CONFIG_CMD_MII
 115 #define CONFIG_CMD_NFS
 116 #define CONFIG_CMD_PING
 117 #define CONFIG_CMD_REGINFO
 118 #define CONFIG_CMD_SNTP
 119 #define CONFIG_CMD_BSP
 120 #define CONFIG_CMD_USB
 121
 122 #ifdef CONFIG_VIDEO
 123 #define CONFIG_CMD_BMP
 124 #endif
 125
 126 #ifdef CONFIG_POST
 127 #define CONFIG__CMD_DIAG
 128 #endif
 129
 130
 131 #define CONFIG_TIMESTAMP                /* display image timestamps */
 132
 133 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 134 #   define CFG_LOWBOOT          1
 135 #endif
 136
 137 /*
 138  * Autobooting
 139  */
 140 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 141
 142 #define CONFIG_PREBOOT  "echo;" \
 143         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 144         "echo"
 145
 146 #undef  CONFIG_BOOTARGS
 147
 148 #if defined(CONFIG_TQM5200_B)
 149 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 150         "netdev=eth0\0"                                                 \
 151         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 152         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 153         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 154                 "nfsroot=${serverip}:${rootpath}\0"                     \
 155         "addip=setenv bootargs ${bootargs} "                            \
 156                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 157                 ":${hostname}:${netdev}:off panic=1\0"                  \
 158         "flash_self=run ramargs addip;"                                 \
 159                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 160         "flash_nfs=run nfsargs addip;"                                  \
 161                 "bootm ${kernel_addr}\0"                                \
 162         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 163         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 164         "load=tftp 200000 ${u-boot}\0"                                  \
 165         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 166         "update=protect off FC000000 FC07FFFF;"                         \
 167                 "erase FC000000 FC07FFFF;"                              \
 168                 "cp.b 200000 FC000000 ${filesize};"                     \
 169                 "protect on FC000000 FC07FFFF\0"                        \
 170         ""
 171 #else
 172 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 173         "netdev=eth0\0"                                                 \
 174         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 175         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 176         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 177                 "nfsroot=${serverip}:${rootpath}\0"                     \
 178         "addip=setenv bootargs ${bootargs} "                            \
 179                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 180                 ":${hostname}:${netdev}:off panic=1\0"                  \
 181         "flash_self=run ramargs addip;"                                 \
 182                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 183         "flash_nfs=run nfsargs addip;"                                  \
 184                 "bootm ${kernel_addr}\0"                                \
 185         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 186         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 187         "load=tftp 200000 $(u-boot)\0"                                  \
 188         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 189         "update=protect off FC000000 FC05FFFF;"                         \
 190                 "erase FC000000 FC05FFFF;"                              \
 191                 "cp.b 200000 FC000000 ${filesize};"                     \
 192                 "protect on FC000000 FC05FFFF\0"                        \
 193         ""
 194 #endif /* CONFIG_TQM5200_B */
 195
 196 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 197
 198 /*
 199  * IPB Bus clocking configuration.
 200  */
 201 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 202
 203 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 204 /*
 205  * PCI Bus clocking configuration
 206  *
 207  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 208  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 209  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 210  */
 211 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2           /* define for 66MHz speed */
 212 #endif
 213
 214 /*
 215  * I2C configuration
 216  */
 217 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 218 #define CFG_I2C_MODULE          2       /* Select I2C module #2 */
 219
 220 /*
 221  * I2C clock frequency
 222  *
 223  * Please notice, that the resulting clock frequency could differ from the
 224  * configured value. This is because the I2C clock is derived from system
 225  * clock over a frequency divider with only a few divider values. U-boot
 226  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 227  * approximation allways lies below the configured value, never above.
 228  */
 229 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 230 #define CFG_I2C_SLAVE           0x7F
 231
 232 /*
 233  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 234  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 235  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 236  * same configuration could be used.
 237  */
 238 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 239 #define CFG_I2C_EEPROM_ADDR_LEN         2
 240 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 241 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 242
 243 /* List of I2C addresses to be verified by POST */
 244 #undef I2C_ADDR_LIST
 245 #define I2C_ADDR_LIST   {       CFG_I2C_EEPROM_ADDR,    \
 246                                 CFG_I2C_RTC_ADDR,       \
 247                                 CFG_I2C_SLAVE }
 248
 249 /*
 250  * Flash configuration
 251  */
 252 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 253
 254 /* use CFI flash driver */
 255 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 256 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 257 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 258 #define CFG_FLASH_EMPTY_INFO
 259 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 260 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 261 #define CFG_FLASH_USE_BUFFER_WRITE      1
 262
 263 #if !defined(CFG_LOWBOOT)
 264 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 265 #else   /* CFG_LOWBOOT */
 266 #if defined(CONFIG_TQM5200_B)
 267 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00080000)
 268 #else
 269 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 270 #endif /* CONFIG_TQM5200_B */
 271 #endif  /* CFG_LOWBOOT */
 272 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 273                                            (= chip selects) */
 274
 275 /* Dynamic MTD partition support */
 276 #define CONFIG_JFFS2_CMDLINE
 277 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 278 #if defined(CONFIG_TQM5200_B)
 279 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:768k(firmware),"    \
 280                                                 "1280k(kernel),"        \
 281                                                 "2m(initrd),"           \
 282                                                 "4m(small-fs),"         \
 283                                                 "16m(big-fs),"          \
 284                                                 "8m(misc)"
 285 #else
 286 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 287                                                 "1408k(kernel),"        \
 288                                                 "2m(initrd),"           \
 289                                                 "4m(small-fs),"         \
 290                                                 "16m(big-fs),"          \
 291                                                 "8m(misc)"
 292 #endif /* CONFIG_TQM5200_B */
 293
 294 /*
 295  * Environment settings
 296  */
 297 #define CFG_ENV_IS_IN_FLASH     1
 298 #define CFG_ENV_SIZE            0x10000
 299 #if defined(CONFIG_TQM5200_B)
 300 #define CFG_ENV_SECT_SIZE       0x40000
 301 #else
 302 #define CFG_ENV_SECT_SIZE       0x20000
 303 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 304 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 305 #endif /* CONFIG_TQM5200_B */
 306
 307 /*
 308  * Memory map
 309  */
 310 #define CFG_MBAR                0xF0000000
 311 #define CFG_SDRAM_BASE          0x00000000
 312 #define CFG_DEFAULT_MBAR        0x80000000
 313
 314 /* Use ON-Chip SRAM until RAM will be available */
 315 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 316 #ifdef CONFIG_POST
 317 /* preserve space for the post_word at end of on-chip SRAM */
 318 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 319 #else
 320 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 321 #endif
 322
 323
 324 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 325 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 326 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 327
 328 #define CFG_MONITOR_BASE        TEXT_BASE
 329 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 330 #   define CFG_RAMBOOT          1
 331 #endif
 332
 333 #if defined(CONFIG_TQM5200_B)
 334 #define CFG_MONITOR_LEN         (512 << 10)     /* Reserve 512 kB for Monitor   */
 335 #else
 336 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 337 #endif /* CONFIG_TQM5200_B */
 338 #define CFG_MALLOC_LEN          (1024 << 10)    /* Reserve 1024 kB for malloc() */
 339 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 340
 341 /*
 342  * Ethernet configuration
 343  */
 344 #define CONFIG_MPC5xxx_FEC      1
 345 /*
 346  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 347  */
 348 /* #define CONFIG_FEC_10MBIT 1 */
 349 #define CONFIG_PHY_ADDR         0x00
 350
 351 /*
 352  * GPIO configuration
 353  *
 354  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 355  *      Bit 0 (mask: 0x80000000): 1
 356  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 357  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 358  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 359  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 360  *            (because, there I2C1 is used as I2C bus)
 361  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 362  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 363  *      000 -> All PSC2 pins are GIOPs
 364  *      001 -> CAN1/2 on PSC2 pins
 365  *             Use for REV100 STK52xx boards
 366  * use PSC3: Bits 20:23 (mask: 0x00000300):
 367  *      0001 -> USB2
 368  *      0000 -> GPIO
 369  * use PSC6:
 370  *   on STK52xx:
 371  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 372  *      Bits 9:11 (mask: 0x00700000):
 373  *         101 -> PSC6 : Extended POST test is not available
 374  *   on MINI-FAP and TQM5200_IB:
 375  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 376  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 377  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 378  *   tests.
 379  */
 380 #define CFG_GPS_PORT_CONFIG     0x81500114
 381
 382 /*
 383  * RTC configuration
 384  */
 385 #define CONFIG_RTC_M41T11       1
 386 #define CFG_I2C_RTC_ADDR        0x68
 387 #define CFG_M41T11_BASE_YEAR    1900    /* because Linux uses the same base
 388                                            year */
 389
 390 /*
 391  * Miscellaneous configurable options
 392  */
 393 #define CFG_LONGHELP                    /* undef to save memory     */
 394 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 395 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 396 #if defined(CONFIG_CMD_KGDB)
 397 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 398 #else
 399 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 400 #endif
 401 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 402 #define CFG_MAXARGS             16      /* max number of command args   */
 403 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 404
 405 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 406 #if defined(CONFIG_CMD_KGDB)
 407 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 408 #endif
 409
 410 /* Enable an alternate, more extensive memory test */
 411 #define CFG_ALT_MEMTEST
 412
 413 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 414 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 415
 416 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 417
 418 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 419
 420 /*
 421  * Enable loopw command.
 422  */
 423 #define CONFIG_LOOPW
 424
 425 /*
 426  * Various low-level settings
 427  */
 428 #if defined(CONFIG_MPC5200)
 429 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 430 #define CFG_HID0_FINAL          HID0_ICE
 431 #else
 432 #define CFG_HID0_INIT           0
 433 #define CFG_HID0_FINAL          0
 434 #endif
 435
 436 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 437 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 438 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 439 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 440 #else
 441 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 442 #endif
 443 #define CFG_CS0_START           CFG_FLASH_BASE
 444 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 445
 446 #define CONFIG_LAST_STAGE_INIT
 447
 448 /*
 449  * SRAM - Do not map below 2 GB in address space, because this area is used
 450  * for SDRAM autosizing.
 451  */
 452 #define CFG_CS2_START           0xE5000000
 453 #define CFG_CS2_SIZE            0x100000        /* 1 MByte */
 454 #define CFG_CS2_CFG             0x0004D930
 455
 456 /*
 457  * Grafic controller - Do not map below 2 GB in address space, because this
 458  * area is used for SDRAM autosizing.
 459  */
 460 #define SM501_FB_BASE           0xE0000000
 461 #define CFG_CS1_START           (SM501_FB_BASE)
 462 #define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
 463 #define CFG_CS1_CFG             0x8F48FF70
 464 #define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
 465
 466 #define CFG_CS_BURST            0x00000000
 467 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 468
 469 #define CFG_RESET_ADDRESS       0xff000000
 470
 471 /*-----------------------------------------------------------------------
 472  * USB stuff
 473  *-----------------------------------------------------------------------
 474  */
 475 #define CONFIG_USB_CLOCK        0x0001BBBB
 476 #define CONFIG_USB_CONFIG       0x00001000
 477
 478 /*-----------------------------------------------------------------------
 479  * IDE/ATA stuff Supports IDE harddisk
 480  *-----------------------------------------------------------------------
 481  */
 482
 483 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 484
 485 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 486 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 487
 488 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 489 #define CONFIG_IDE_PREINIT
 490
 491 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 492 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 493
 494 #define CFG_ATA_IDE0_OFFSET     0x0000
 495
 496 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 497
 498 /* Offset for data I/O                  */
 499 #define CFG_ATA_DATA_OFFSET     (0x0060)
 500
 501 /* Offset for normal register accesses  */
 502 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 503
 504 /* Offset for alternate registers       */
 505 #define CFG_ATA_ALT_OFFSET      (0x005C)
 506
 507 /* Interval between registers                                                */
 508 #define CFG_ATA_STRIDE          4
 509
 510 #endif /* __CONFIG_H */