include/configs/KUP4K.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  * Derived from ../tqm8xx/tqm8xx.c
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  39 #define CONFIG_KUP4K            1       /* ...on a KUP4K module */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate             */
  45 #if 0
  46 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  47 #else
  48 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  49 #endif
  50
  51 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  52
  53
  54 #undef  CONFIG_BOOTARGS
  55
  56
  57 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
  58 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"                            \
  59  "run addhw; diskboot 200000 0:1; bootm 200000\0"                               \
  60 "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"                            \
  61  "run addhw; diskboot 200000 2:1; bootm 200000\0"                               \
  62 "nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0"                        \
  63 "panic_boot=echo No Bootdevice !!! reset\0"                                     \
  64 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
  65 "ramargs=setenv bootargs root=/dev/ram rw\0"                                    \
  66 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"       \
  67  ":${netmask}:${hostname}:${netdev}:off\0"                                      \
  68 "addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"             \
  69 "netdev=eth0\0"                                                                 \
  70 "contrast=55\0"                                                                 \
  71 "silent=1\0"                                                                    \
  72 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"         \
  73 "update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};"          \
  74  "cp.b 200000 40050000 14000\0"
  75
  76 #define CONFIG_BOOTCOMMAND  \
  77     "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
  78
  79
  80 #define CONFIG_MISC_INIT_R      1
  81 #define CONFIG_MISC_INIT_F      1
  82
  83 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  84 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  85
  86 #define CONFIG_WATCHDOG 1               /* watchdog enabled             */
  87
  88 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  89
  90 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  91
  92 /*
  93  * BOOTP options
  94  */
  95 #define CONFIG_BOOTP_SUBNETMASK
  96 #define CONFIG_BOOTP_GATEWAY
  97 #define CONFIG_BOOTP_HOSTNAME
  98 #define CONFIG_BOOTP_BOOTPATH
  99 #define CONFIG_BOOTP_BOOTFILESIZE
 100
 101
 102 #define CONFIG_MAC_PARTITION
 103 #define CONFIG_DOS_PARTITION
 104
 105
 106 /*
 107  * enable I2C and select the hardware/software driver
 108  */
 109 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 110 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 111
 112 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 113 #define CFG_I2C_SLAVE           0xFE
 114
 115 #ifdef CONFIG_SOFT_I2C
 116 /*
 117  * Software (bit-bang) I2C driver configuration
 118  */
 119 #define PB_SCL          0x00000020      /* PB 26 */
 120 #define PB_SDA          0x00000010      /* PB 27 */
 121
 122 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 123 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 124 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 125 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 126 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 127                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 128 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 129                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 130 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 131 #endif  /* CONFIG_SOFT_I2C */
 132
 133
 134 /*-----------------------------------------------------------------------
 135  * I2C Configuration
 136  */
 137
 138 #define CFG_I2C_PICIO_ADDR      0x21    /* PCF8574 IO Expander                  */
 139 #define CFG_I2C_RTC_ADDR        0x51    /* PCF8563 RTC                          */
 140
 141
 142 /* List of I2C addresses to be verified by POST */
 143
 144 #define I2C_ADDR_LIST   {CFG_I2C_PICIO_ADDR,    \
 145                         CFG_I2C_RTC_ADDR,       \
 146                         }
 147
 148
 149 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 150
 151 #define CFG_DISCOVER_PHY
 152 #define CONFIG_MII
 153
 154 #if 0
 155 #define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
 156 #endif
 157 #define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */
 158
 159 /* Define to allow the user to overwrite serial and ethaddr */
 160 #define CONFIG_ENV_OVERWRITE
 161 #if 1
 162 /* POST support */
 163
 164 #define CONFIG_POST             (CFG_POST_CPU      | \
 165                                  CFG_POST_RTC      | \
 166                                  CFG_POST_I2C)
 167 #endif
 168
 169
 170 /*
 171  * Command line configuration.
 172  */
 173 #include <config_cmd_default.h>
 174
 175 #define CONFIG_CMD_DATE
 176 #define CONFIG_CMD_DHCP
 177 #define CONFIG_CMD_I2C
 178 #define CONFIG_CMD_IDE
 179 #define CONFIG_CMD_NFS
 180 #define CONFIG_CMD_SNTP
 181
 182 #ifdef CONFIG_POST
 183     #define CONFIG_CMD_DIAG
 184 #endif
 185
 186 /*
 187  * Miscellaneous configurable options
 188  */
 189 #define CFG_LONGHELP                    /* undef to save memory         */
 190 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 191 #if defined(CONFIG_CMD_KGDB)
 192 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 193 #else
 194 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 195 #endif
 196 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 197 #define CFG_MAXARGS     16              /* max number of command args   */
 198 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 199
 200 #define CFG_MEMTEST_START       0x000400000     /* memtest works on     */
 201 #define CFG_MEMTEST_END         0x002C00000     /* 4 ... 44 MB in DRAM  */
 202
 203 #define CFG_LOAD_ADDR           0x200000        /* default load address */
 204
 205 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 206
 207 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 115200 }
 208
 209 #define CFG_CONSOLE_INFO_QUIET 1
 210
 211 /*
 212  * Low Level Configuration Settings
 213  * (address mappings, register initial values, etc.)
 214  * You should know what you are doing if you make changes here.
 215  */
 216 /*-----------------------------------------------------------------------
 217  * Internal Memory Mapped Register
 218  */
 219 #define CFG_IMMR                0xFFF00000
 220
 221 /*-----------------------------------------------------------------------
 222  * Definitions for initial stack pointer and data area (in DPRAM)
 223  */
 224 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 225 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 226 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 227 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 228 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 229
 230 /*-----------------------------------------------------------------------
 231  * Start addresses for the final memory configuration
 232  * (Set up by the startup code)
 233  * Please note that CFG_SDRAM_BASE _must_ start at 0
 234  */
 235 #define CFG_SDRAM_BASE          0x00000000
 236 #define CFG_FLASH_BASE          0x40000000
 237 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 238 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 239 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 240
 241 /*
 242  * For booting Linux, the board info and command line data
 243  * have to be in the first 8 MB of memory, since this is
 244  * the maximum mapped by the Linux kernel during initialization.
 245  */
 246 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 247
 248 /*-----------------------------------------------------------------------
 249  * FLASH organization
 250  */
 251 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 252 #define CFG_MAX_FLASH_SECT      19      /* max number of sectors on one chip    */
 253
 254 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 255 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 256
 257 #define CFG_ENV_IS_IN_FLASH     1
 258 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 259 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector     */
 260 #define CFG_ENV_SECT_SIZE       0x10000
 261
 262 /* Address and size of Redundant Environment Sector     */
 263 #if 0
 264 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 265 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 266 #endif
 267 /*-----------------------------------------------------------------------
 268  * Hardware Information Block
 269  */
 270 #if 1
 271 #define CFG_HWINFO_OFFSET       0x000F0000      /* offset of HW Info block */
 272 #define CFG_HWINFO_SIZE         0x00000100      /* size   of HW Info block */
 273 #define CFG_HWINFO_MAGIC        0x4B26500D      /* 'K&P<CR>' */
 274 #endif
 275 /*-----------------------------------------------------------------------
 276  * Cache Configuration
 277  */
 278 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 279 #if defined(CONFIG_CMD_KGDB)
 280 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 281 #endif
 282
 283 /*-----------------------------------------------------------------------
 284  * SYPCR - System Protection Control                            11-9
 285  * SYPCR can only be written once after reset!
 286  *-----------------------------------------------------------------------
 287  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 288  */
 289 #if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 290 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 291                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 292 #else
 293 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 294 #endif
 295
 296 /*-----------------------------------------------------------------------
 297  * SIUMCR - SIU Module Configuration                            11-6
 298  *-----------------------------------------------------------------------
 299  * PCMCIA config., multi-function pin tri-state
 300  */
 301 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 302
 303 /*-----------------------------------------------------------------------
 304  * TBSCR - Time Base Status and Control                         11-26
 305  *-----------------------------------------------------------------------
 306  * Clear Reference Interrupt Status, Timebase freezing enabled
 307  */
 308 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 309
 310 /*-----------------------------------------------------------------------
 311  * RTCSC - Real-Time Clock Status and Control Register          11-27
 312  *-----------------------------------------------------------------------
 313  */
 314 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 315
 316 /*-----------------------------------------------------------------------
 317  * PISCR - Periodic Interrupt Status and Control                11-31
 318  *-----------------------------------------------------------------------
 319  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 320  */
 321 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 322
 323 /*-----------------------------------------------------------------------
 324  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 325  *-----------------------------------------------------------------------
 326  * Reset PLL lock status sticky bit, timer expired status bit and timer
 327  * interrupt status bit
 328  *
 329  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 330  */
 331 #define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 332
 333 /*-----------------------------------------------------------------------
 334  * SCCR - System Clock and reset Control Register               15-27
 335  *-----------------------------------------------------------------------
 336  * Set clock output, timebase and RTC source and divider,
 337  * power management and some other internal clocks
 338  */
 339 #define SCCR_MASK       SCCR_EBDF00
 340 #define CFG_SCCR        (SCCR_TBS | SCCR_EBDF01 |  \
 341                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 342                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 343                          SCCR_DFALCD00)
 344
 345 /*-----------------------------------------------------------------------
 346  * PCMCIA stuff
 347  *-----------------------------------------------------------------------
 348  *
 349  */
 350
 351 /* KUP4K use both slots, SLOT_A as "primary". */
 352 #define CONFIG_PCMCIA_SLOT_A 1
 353
 354 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 355 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 356 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 357 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 358 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 359 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 360 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 361 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 362
 363 #define PCMCIA_SOCKETS_NO 2
 364 #define PCMCIA_MEM_WIN_NO 8
 365 /*-----------------------------------------------------------------------
 366  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 367  *-----------------------------------------------------------------------
 368  */
 369
 370 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 371
 372 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 373 #define CONFIG_IDE_LED          1       /* LED   for ide supported      */
 374 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 375
 376 #define CFG_IDE_MAXBUS          2
 377 #define CFG_IDE_MAXDEVICE       4
 378
 379 #define CFG_ATA_IDE0_OFFSET     0x0000
 380
 381 #define CFG_ATA_IDE1_OFFSET     (4 * CFG_PCMCIA_MEM_SIZE)
 382
 383 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 384
 385 /* Offset for data I/O                  */
 386 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 387
 388 /* Offset for normal register accesses  */
 389 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 390
 391 /* Offset for alternate registers       */
 392 #define CFG_ATA_ALT_OFFSET      0x0100
 393
 394
 395 /*-----------------------------------------------------------------------
 396  *
 397  *-----------------------------------------------------------------------
 398  *
 399  */
 400 #define CFG_DER 0
 401
 402 /*
 403  * Init Memory Controller:
 404  *
 405  * BR0/1 and OR0/1 (FLASH)
 406  */
 407 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 408
 409 /* used to re-map FLASH both when starting from SRAM or FLASH:
 410  * restrict access enough to keep SRAM working (if any)
 411  * but not too much to meddle with FLASH accesses
 412  */
 413 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 414 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 415
 416 /*
 417  * FLASH timing:
 418  */
 419 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 420                                  OR_SCY_2_CLK | OR_EHTR | OR_BI)
 421
 422 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 423 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 424 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 425
 426
 427 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 428 #define CFG_OR_TIMING_SDRAM     0x00000A00
 429
 430
 431 /*
 432  * Memory Periodic Timer Prescaler
 433  *
 434  * The Divider for PTA (refresh timer) configuration is based on an
 435  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 436  * the number of chip selects (NCS) and the actually needed refresh
 437  * rate is done by setting MPTPR.
 438  *
 439  * PTA is calculated from
 440  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 441  *
 442  *      gclk      CPU clock (not bus clock!)
 443  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 444  *
 445  * 4096  Rows from SDRAM example configuration
 446  * 1000  factor s -> ms
 447  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 448  *    4  Number of refresh cycles per period
 449  *   64  Refresh cycle in ms per number of rows
 450  * --------------------------------------------
 451  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 452  *
 453  * 50 MHz => 50.000.000 / Divider =  98
 454  * 66 Mhz => 66.000.000 / Divider = 129
 455  * 80 Mhz => 80.000.000 / Divider = 156
 456  */
 457 #if   defined(CONFIG_80MHz)
 458 #define CFG_MAMR_PTA            156
 459 #elif defined(CONFIG_66MHz)
 460 #define CFG_MAMR_PTA            129
 461 #else           /*   50 MHz */
 462 #define CFG_MAMR_PTA             98
 463 #endif  /*CONFIG_??MHz */
 464
 465 /*
 466  * For 16 MBit, refresh rates could be 31.3 us
 467  * (= 64 ms / 2K = 125 / quad bursts).
 468  * For a simpler initialization, 15.6 us is used instead.
 469  *
 470  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 471  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 472  */
 473 #define CFG_MPTPR 0x400
 474
 475 /*
 476  * MAMR settings for SDRAM
 477  */
 478 #define CFG_MAMR 0x80802114
 479
 480 /*
 481  * Internal Definitions
 482  *
 483  * Boot Flags
 484  */
 485 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 486 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 487
 488
 489 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 490 #if 0
 491 #define CONFIG_AUTOBOOT_PROMPT          "Boote in %d Sekunden - stop mit \"2\"\n"
 492 #endif
 493 #define CONFIG_AUTOBOOT_STOP_STR        "." /* easy to stop for now */
 494 #define CONFIG_SILENT_CONSOLE   1
 495
 496 #endif  /* __CONFIG_H */