include/configs/ISPAN.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Interphase iSPAN Communications Controllers
   6  * (453x and others). Tested on 4532.
   7  *
   8  * Derived from iSPAN 4539 port (iphase4539) by
   9  * Wolfgang Grandegger <wg@denx.de>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 #define CONFIG_MPC8260                  /* This is an MPC8260 CPU               */
  33 #define CONFIG_ISPAN                    /* ...on one of Interphase iSPAN boards */
  34 #define CONFIG_CPM2             1       /* Has a CPM2 */
  35
  36 /*-----------------------------------------------------------------------
  37  * Select serial console configuration
  38  *
  39  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  40  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  41  * for SCC).
  42  *
  43  * If CONFIG_CONS_NONE is defined, then the serial console routines must be
  44  * defined elsewhere (for example, on the cogent platform, there are serial
  45  * ports on the motherboard which are used for the serial console - see
  46  * cogent/cma101/serial.[ch]).
  47  */
  48 #define CONFIG_CONS_ON_SMC              /* Define if console on SMC             */
  49 #undef  CONFIG_CONS_ON_SCC              /* Define if console on SCC             */
  50 #undef  CONFIG_CONS_NONE                /* Define if console on something else  */
  51 #define CONFIG_CONS_INDEX       1       /* Which serial channel for console     */
  52
  53 /*-----------------------------------------------------------------------
  54  * Select Ethernet configuration
  55  *
  56  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  57  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  58  * for FCC).
  59  *
  60  * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
  61  * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  62  */
  63 #undef  CONFIG_ETHER_ON_SCC             /* Define if Ethernet on SCC            */
  64 #define CONFIG_ETHER_ON_FCC             /* Define if Ethernet on FCC            */
  65 #undef  CONFIG_ETHER_NONE               /* Define if Ethernet on something else */
  66 #define CONFIG_ETHER_INDEX      3       /* Which channel for Ethernrt           */
  67
  68 #ifdef CONFIG_ETHER_ON_FCC
  69
  70 #if CONFIG_ETHER_INDEX == 3
  71
  72 #define CFG_PHY_ADDR            0
  73 #define CFG_CMXFCR_VALUE        (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
  74 #define CFG_CMXFCR_MASK         (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  75
  76 #endif /* CONFIG_ETHER_INDEX == 3 */
  77
  78 #define CFG_CPMFCR_RAMTYPE      0
  79 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
  80
  81 #define CONFIG_MII                              /* MII PHY management           */
  82 #define CONFIG_BITBANGMII                       /* Bit-bang MII PHY management  */
  83 /*
  84  * GPIO pins used for bit-banged MII communications
  85  */
  86 #define MDIO_PORT               3               /* Port D */
  87
  88 #define CFG_MDIO_PIN            0x00040000      /* PD13 */
  89 #define CFG_MDC_PIN             0x00080000      /* PD12 */
  90
  91 #define MDIO_ACTIVE             (iop->pdir |=  CFG_MDIO_PIN)
  92 #define MDIO_TRISTATE           (iop->pdir &= ~CFG_MDIO_PIN)
  93 #define MDIO_READ               ((iop->pdat &  CFG_MDIO_PIN) != 0)
  94
  95 #define MDIO(bit)               if(bit) iop->pdat |=  CFG_MDIO_PIN; \
  96                                 else    iop->pdat &= ~CFG_MDIO_PIN
  97
  98 #define MDC(bit)                if(bit) iop->pdat |=  CFG_MDC_PIN; \
  99                                 else    iop->pdat &= ~CFG_MDC_PIN
 100
 101 #define MIIDELAY                udelay(1)
 102
 103 #endif /* CONFIG_ETHER_ON_FCC */
 104
 105 #define CONFIG_8260_CLKIN       65536000        /* in Hz */
 106 #define CONFIG_BAUDRATE         38400
 107
 108
 109 /*
 110  * BOOTP options
 111  */
 112 #define CONFIG_BOOTP_BOOTFILESIZE
 113 #define CONFIG_BOOTP_BOOTPATH
 114 #define CONFIG_BOOTP_GATEWAY
 115 #define CONFIG_BOOTP_HOSTNAME
 116
 117
 118 /*
 119  * Command line configuration.
 120  */
 121 #include <config_cmd_default.h>
 122
 123 #define CONFIG_CMD_ASKENV
 124 #define CONFIG_CMD_DHCP
 125 #define CONFIG_CMD_IMMAP
 126 #define CONFIG_CMD_MII
 127 #define CONFIG_CMD_PING
 128 #define CONFIG_CMD_REGINFO
 129
 130
 131 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds     */
 132 #define CONFIG_BOOTCOMMAND      "bootm fe010000"        /* autoboot command     */
 133 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 134
 135 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
 136 #undef  CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
 137
 138 /*-----------------------------------------------------------------------
 139  * Miscellaneous configurable options
 140  */
 141 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 142 #define CFG_HUSH_PARSER
 143 #define CFG_PROMPT_HUSH_PS2     "> "
 144 #define CFG_LONGHELP                            /* #undef to save memory        */
 145 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 146 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
 147 #define CFG_MAXARGS             16              /* Max number of command args   */
 148 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 149
 150 #define CFG_MEMTEST_START       0x00100000      /* memtest works on             */
 151 #define CFG_MEMTEST_END         0x03B00000      /* 1 ... 59 MB in SDRAM         */
 152
 153 #define CFG_LOAD_ADDR           0x100000        /* Default load address         */
 154
 155 #define CFG_HZ                  1000            /* Decrementer freq: 1 ms ticks */
 156
 157 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 158
 159 #define CFG_RESET_ADDRESS       0x09900000
 160
 161 #define CONFIG_MISC_INIT_R                      /* We need misc_init_r()        */
 162
 163 /*-----------------------------------------------------------------------
 164  * For booting Linux, the board info and command line data
 165  * have to be in the first 8 MB of memory, since this is
 166  * the maximum mapped by the Linux kernel during initialization.
 167  */
 168 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 169
 170 #define CFG_MONITOR_BASE        TEXT_BASE
 171 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 172 #ifdef CONFIG_BZIP2
 173 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 174 #else
 175 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 176 #endif /* CONFIG_BZIP2 */
 177
 178 /*-----------------------------------------------------------------------
 179  * FLASH organization
 180  */
 181 #define CFG_FLASH_BASE          0xFE000000
 182 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 183 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 184 #define CFG_MAX_FLASH_BANKS     1               /* Max num of memory banks      */
 185 #define CFG_MAX_FLASH_SECT      142             /* Max num of sects on one chip */
 186
 187 /* Environment is in flash, there is little space left in Serial EEPROM */
 188 #define CFG_ENV_IS_IN_FLASH
 189 #define CFG_ENV_SECT_SIZE       0x10000         /* We use one complete sector   */
 190 #define CFG_ENV_SIZE            (CFG_ENV_SECT_SIZE)
 191 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 192 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 193 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 194
 195 /*-----------------------------------------------------------------------
 196  * Hard Reset Configuration Words
 197  *
 198  * If you change bits in the HRCW, you must also change the CFG_*
 199  * defines for the various registers affected by the HRCW e.g. changing
 200  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 201  */
 202 /* 0x1686B245 */
 203 #define CFG_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
 204                          HRCW_L2CPC10  | HRCW_ISB110                    |\
 205                          HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
 206                          HRCW_CS10PC01 | HRCW_MODCK_H0101                \
 207                         )
 208 /* No slaves */
 209 #define CFG_HRCW_SLAVE1 0
 210 #define CFG_HRCW_SLAVE2 0
 211 #define CFG_HRCW_SLAVE3 0
 212 #define CFG_HRCW_SLAVE4 0
 213 #define CFG_HRCW_SLAVE5 0
 214 #define CFG_HRCW_SLAVE6 0
 215 #define CFG_HRCW_SLAVE7 0
 216
 217 /*-----------------------------------------------------------------------
 218  * Internal Memory Mapped Register
 219  */
 220 #define CFG_IMMR                0xF0F00000
 221 #ifdef CFG_REV_B
 222 #define CFG_DEFAULT_IMMR        0xFF000000
 223 #endif /* CFG_REV_B */
 224 /*-----------------------------------------------------------------------
 225  * Definitions for initial stack pointer and data area (in DPRAM)
 226  */
 227 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 228 #define CFG_INIT_RAM_END        0x4000          /* End of used area in DPRAM    */
 229 #define CFG_GBL_DATA_SIZE       128  /* Size in bytes reserved for initial data */
 230 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 231 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 232
 233 /*-----------------------------------------------------------------------
 234  * Internal Definitions
 235  *
 236  * Boot Flags
 237  */
 238 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from flash     */
 239 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 240
 241 /*-----------------------------------------------------------------------
 242  * Cache Configuration
 243  */
 244 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU                      */
 245
 246 /*-----------------------------------------------------------------------
 247  * HIDx - Hardware Implementation-dependent Registers           2-11
 248  *-----------------------------------------------------------------------
 249  * HID0 also contains cache control.
 250  *
 251  * HID1 has only read-only information - nothing to set.
 252  */
 253 #define CFG_HID0_INIT           (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 254                                 HID0_IFEM|HID0_ABE)
 255 #define CFG_HID0_FINAL          (HID0_ICE|HID0_IFEM|HID0_ABE)
 256 #define CFG_HID2                0
 257
 258 /*-----------------------------------------------------------------------
 259  * RMR - Reset Mode Register                                     5-5
 260  *-----------------------------------------------------------------------
 261  * turn on Checkstop Reset Enable
 262  */
 263 #define CFG_RMR                 RMR_CSRE
 264
 265 /*-----------------------------------------------------------------------
 266  * BCR - Bus Configuration                                       4-25
 267  *-----------------------------------------------------------------------
 268  */
 269 #define CFG_BCR                 0xA01C0000
 270
 271 /*-----------------------------------------------------------------------
 272  * SIUMCR - SIU Module Configuration                             4-31
 273  *-----------------------------------------------------------------------
 274  */
 275 #define CFG_SIUMCR              0x42250000/* 0x4205C000 */
 276
 277 /*-----------------------------------------------------------------------
 278  * SYPCR - System Protection Control                             4-35
 279  * SYPCR can only be written once after reset!
 280  *-----------------------------------------------------------------------
 281  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 282  */
 283 #if defined (CONFIG_WATCHDOG)
 284 #define CFG_SYPCR               (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 285                                 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 286 #else
 287 #define CFG_SYPCR               (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 288                                 SYPCR_SWRI|SYPCR_SWP)
 289 #endif /* CONFIG_WATCHDOG */
 290
 291 /*-----------------------------------------------------------------------
 292  * TMCNTSC - Time Counter Status and Control                     4-40
 293  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 294  * and enable Time Counter
 295  *-----------------------------------------------------------------------
 296  */
 297 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 298
 299 /*-----------------------------------------------------------------------
 300  * PISCR - Periodic Interrupt Status and Control                 4-42
 301  *-----------------------------------------------------------------------
 302  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 303  * Periodic timer
 304  */
 305 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 306
 307 /*-----------------------------------------------------------------------
 308  * SCCR - System Clock Control                                   9-8
 309  *-----------------------------------------------------------------------
 310  * Ensure DFBRG is Divide by 16
 311  */
 312 #define CFG_SCCR                SCCR_DFBRG01
 313
 314 /*-----------------------------------------------------------------------
 315  * RCCR - RISC Controller Configuration                         13-7
 316  *-----------------------------------------------------------------------
 317  */
 318 #define CFG_RCCR                0
 319
 320 /*-----------------------------------------------------------------------
 321  * Init Memory Controller:
 322  *
 323  * Bank Bus     Machine PortSize                        Device
 324  * ---- ---     ------- -----------------------------   ------
 325  *  0   60x     GPCM     8 bit (Rev.B)/16 bit (Rev.D)   Flash
 326  *  1   60x     SDRAM   64 bit                          SDRAM
 327  *  2   Local   SDRAM   32 bit                          SDRAM
 328  */
 329 #define CFG_USE_FIRMWARE        /* If defined - do not initialise memory
 330                                    controller, rely on initialisation
 331                                    performed by the Interphase boot firmware.
 332                                  */
 333
 334 #define CFG_OR0_PRELIM          0xFE000882
 335 #ifdef CFG_REV_B
 336 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BRx_PS_8  | BRx_V)
 337 #else  /* Rev. D */
 338 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
 339 #endif /* CFG_REV_B */
 340
 341 #define CFG_MPTPR               0x7F00
 342
 343 /* Please note that 60x SDRAM MUST start at 0 */
 344 #define CFG_SDRAM_BASE          0x00000000
 345 #define CFG_60x_BR              0x00000041
 346 #define CFG_60x_OR              0xF0002CD0
 347 #define CFG_PSDMR               0x0049929A
 348 #define CFG_PSRT                0x07
 349
 350 #define CFG_LSDRAM_BASE         0xF7000000
 351 #define CFG_LOC_BR              0x00001861
 352 #define CFG_LOC_OR              0xFF803280
 353 #define CFG_LSDMR               0x8285A552
 354 #define CFG_LSRT                0x07
 355
 356 #endif /* __CONFIG_H */