include/configs/IAD210.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #include <mpc8xx_irq.h>
  32
  33
  34 # ifdef DEBUG
  35 #  warning DEBUG Defined
  36 # endif /* DEBUG */
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42 #define CONFIG_MPC860           1
  43 #define CONFIG_IAD210           1       /* ...on a IAD210  module       */
  44 #define CONFIG_MPC860T          1
  45 #define CONFIG_MPC862           1
  46
  47 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  48
  49 #undef  CONFIG_8xx_CONS_SMC1
  50 #undef  CONFIG_8xx_CONS_SMC2
  51 #define CONFIG_8xx_CONS_SCC2   /* V24 on SCC2 */
  52 #undef  CONFIG_8xx_CONS_NONE
  53 #define CONFIG_BAUDRATE         9600
  54
  55
  56 # define MPC8XX_FACT            16
  57 # define CONFIG_8xx_GCLK_FREQ   (64000000L)  /* define if can't use get_gclk_freq */
  58 # define CONFIG_CLOCKS_IN_MHZ   1            /* clocks passsed to Linux in MHz */
  59
  60 #if 0
  61 # define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
  62 #else
  63 # define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
  64 #endif
  65
  66 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  67
  68 /* using this define saves us updating another source file */
  69 #define CONFIG_BOARD_EARLY_INIT_F 1
  70
  71 #undef  CONFIG_BOOTARGS
  72 /* #define CONFIG_BOOTCOMMAND                                                   \
  73         "bootp;"                                                                \
  74         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  75         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  76         "bootm"
  77 */
  78
  79 #define CONFIG_BOOTCOMMAND      \
  80         "setenv bootargs root=/dev/nfs"         \
  81         "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; "        \
  82
  83 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  84
  85 /* #define      CONFIG_STATUS_LED       1*/     /* Status LED enabled           */
  86
  87 /*
  88  * BOOTP options
  89  */
  90 #define CONFIG_BOOTP_SUBNETMASK
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95
  96
  97 # undef  CONFIG_SCC1_ENET               /* disable SCC1 ethernet */
  98 # define CONFIG_FEC_ENET    1   /* use FEC ethernet  */
  99 # define CONFIG_MII         1
 100 # define CFG_DISCOVER_PHY   1
 101 # define CONFIG_FEC_UTOPIA  1
 102 # define CONFIG_ETHADDR     08:00:06:26:A2:6D
 103 # define CONFIG_IPADDR      192.168.28.128
 104 # define CONFIG_SERVERIP    139.10.137.138
 105 # define CFG_DISCOVER_PHY   1
 106
 107 #define CONFIG_MAC_PARTITION
 108 #define CONFIG_DOS_PARTITION
 109
 110 /* enable I2C and select the hardware/software driver */
 111 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 112 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 113 # define CFG_I2C_SPEED          50000
 114 # define CFG_I2C_SLAVE          0xDD
 115 # define CFG_I2C_EEPROM_ADDR    0x50
 116 /*
 117  * Software (bit-bang) I2C driver configuration
 118  */
 119 #define PB_SCL          0x00000020      /* PB 26 */
 120 #define PB_SDA          0x00000010      /* PB 27 */
 121
 122 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 123 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 124 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 125 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 126 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 127                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 128 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 129                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 130 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 131
 132 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 133
 134
 135 /*
 136  * Command line configuration.
 137  */
 138 #include <config_cmd_default.h>
 139
 140 #define CONFIG_CMD_ASKENV
 141 #define CONFIG_CMD_DHCP
 142 #define CONFIG_CMD_DATE
 143
 144
 145 /*
 146  * Miscellaneous configurable options
 147  */
 148 #define CFG_LONGHELP                    /* undef to save memory         */
 149 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 150 #if defined(CONFIG_CMD_KGDB)
 151 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 152 #else
 153 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 154 #endif
 155 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 156 #define CFG_MAXARGS     16              /* max number of command args   */
 157 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 158
 159 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 160 #define CFG_MEMTEST_END         0x0400000       /* 1 ... 4 MB in DRAM   */
 161
 162 #define CFG_LOAD_ADDR           0x00100000
 163
 164 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 165
 166 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 167
 168 /*
 169  * Low Level Configuration Settings
 170  * (address mappings, register initial values, etc.)
 171  * You should know what you are doing if you make changes here.
 172  */
 173 /*-----------------------------------------------------------------------
 174  * Internal Memory Mapped Register
 175  */
 176 #define CFG_IMMR                0xFFF00000
 177 #define CFG_IMMR_SIZE           ((uint)(64 * 1024))
 178
 179 /*-----------------------------------------------------------------------
 180  * Definitions for initial stack pointer and data area (in DPRAM)
 181  */
 182 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 183 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 184 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 185 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 186 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 187
 188 /*-----------------------------------------------------------------------
 189  * Start addresses for the final memory configuration
 190  * (Set up by the startup code)
 191  * Please note that CFG_SDRAM_BASE _must_ start at 0
 192  */
 193 #define CFG_SDRAM_BASE          0x00000000
 194 #define CFG_FLASH_BASE          0x08000000
 195 #define CFG_FLASH_SIZE          ((uint)(4 * 1024 * 1024))       /* max 16Mbyte */
 196
 197 #define CFG_RESET_ADDRESS       0xFFF00100
 198
 199 #if defined(DEBUG)
 200 # define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 201 #else
 202 # define        CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 203 #endif
 204
 205 # define CFG_MONITOR_BASE       CFG_FLASH_BASE
 206 # define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 kB for malloc()  */
 207
 208 /*
 209  * For booting Linux, the board info and command line data
 210  * have to be in the first 8 MB of memory, since this is
 211  * the maximum mapped by the Linux kernel during initialization.
 212  */
 213 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 214 /*-----------------------------------------------------------------------
 215  * FLASH organization
 216  */
 217 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 218 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip    */
 219
 220 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 221 #define CFG_FLASH_WRITE_TOUT    500             /* Timeout for Flash Write (in ms)      */
 222
 223 #define CFG_ENV_IS_IN_FLASH     1
 224 #define CFG_ENV_OFFSET          0x8000
 225 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 226
 227 /*-----------------------------------------------------------------------
 228  * Cache Configuration
 229  */
 230 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 231 #if defined(CONFIG_CMD_KGDB)
 232 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 233 #endif
 234
 235 /*-----------------------------------------------------------------------
 236  * SYPCR - System Protection Control                                    11-9
 237  * SYPCR can only be written once after reset!
 238  *-----------------------------------------------------------------------
 239  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 240  */
 241 #if defined(CONFIG_WATCHDOG)
 242 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 243                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 244 #else
 245 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 246 #endif
 247
 248 /*-----------------------------------------------------------------------
 249  * SIUMCR - SIU Module Configuration                                    11-6
 250  *-----------------------------------------------------------------------
 251  * PCMCIA config., multi-function pin tri-state
 252  */
 253 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 254
 255 /*-----------------------------------------------------------------------
 256  * TBSCR - Time Base Status and Control                                 11-26
 257  *-----------------------------------------------------------------------
 258  * Clear Reference Interrupt Status, Timebase freezing enabled
 259  */
 260 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 261
 262 /*-----------------------------------------------------------------------
 263  * PISCR - Periodic Interrupt Status and Control                11-31
 264  *-----------------------------------------------------------------------
 265  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 266  */
 267 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 268
 269 /*-----------------------------------------------------------------------
 270  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 271  *-----------------------------------------------------------------------
 272  * set the PLL, the low-power modes and the reset control (15-29)
 273  */
 274 #define CFG_PLPRCR      (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 275                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 276
 277 /*-----------------------------------------------------------------------
 278  * SCCR - System Clock and reset Control Register               15-27
 279  *-----------------------------------------------------------------------
 280  * Set clock output, timebase and RTC source and divider,
 281  * power management and some other internal clocks
 282  */
 283 #define SCCR_MASK       SCCR_EBDF11
 284
 285 #define CFG_SCCR        (SCCR_TBS       | SCCR_COM00    | SCCR_DFSYNC00 | \
 286                          SCCR_DFBRG00   | SCCR_DFNL000  | SCCR_DFNH000  | \
 287                          SCCR_DFLCD000  |SCCR_DFALCD00  )
 288
 289 /*-----------------------------------------------------------------------
 290  * RCCR - RISC Controller Configuration Register                19-4
 291  *-----------------------------------------------------------------------
 292  */
 293 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
 294 #define CFG_RCCR 0x0020
 295
 296 /*-----------------------------------------------------------------------
 297  * PCMCIA stuff
 298  *-----------------------------------------------------------------------
 299  */
 300 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 301 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 302
 303 /*-----------------------------------------------------------------------
 304  *
 305  *-----------------------------------------------------------------------
 306  *
 307  */
 308 #define CFG_DER         0
 309
 310 /* Because of the way the 860 starts up and assigns CS0 the
 311 * entire address space, we have to set the memory controller
 312 * differently.  Normally, you write the option register
 313 * first, and then enable the chip select by writing the
 314 * base register.  For CS0, you must write the base register
 315 * first, followed by the option register.
 316 */
 317
 318 /*
 319  * Init Memory Controller:
 320  *
 321  * BR0 and OR0 (FLASH)
 322  */
 323
 324 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
 325
 326 /* used to re-map FLASH both when starting from SRAM or FLASH:
 327  * restrict access enough to keep SRAM working (if any)
 328  * but not too much to meddle with FLASH accesses
 329  */
 330 #define CFG_REMAP_OR_AM         0xF8000000      /* OR addr mask */
 331 #define CFG_PRELIM_OR_AM        0xF8000000      /* OR addr mask */
 332
 333 /* FLASH timing:
 334  TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1  */
 335 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
 336                                  OR_SCY_3_CLK | OR_EHTR)
 337
 338 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 339 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 340
 341 /*
 342  * BR2/3 and OR2/3 (SDRAM)
 343  *
 344  */
 345 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM bank #0        */
 346 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 347
 348 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 349
 350 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | OR_CSNT_SAM  | OR_BI | OR_ACS_DIV4)
 351 #define CFG_BR2_PRELIM  ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 352 #define CFG_BR1_PRELIM  ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 353
 354 /*
 355  * Memory Periodic Timer Prescaler
 356  */
 357
 358 /* periodic timer for refresh */
 359 #define CFG_MAMR_PTA    124             /* start with divider for 64 MHz        */
 360
 361 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 362 #define CFG_MPTPR               MPTPR_PTP_DIV32         /* setting for 1 bank   */
 363
 364 /*
 365  * MAMR settings for SDRAM
 366  */
 367
 368 #define CFG_MAMR        ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 369                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 370                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_8X)
 371
 372
 373 /*
 374  * Internal Definitions
 375  *
 376  * Boot Flags
 377  */
 378 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 379 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 380
 381 #ifdef CONFIG_MPC860T
 382
 383 /* Interrupt level assignments.
 384 */
 385 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 386
 387 #endif /* CONFIG_MPC860T */
 388
 389
 390 #endif  /* __CONFIG_H */