include/configs/ASH405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_ASH405           1       /* ...on a ASH405 board         */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33333300 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #undef  CONFIG_BOOTCOMMAND
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  54 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  55
  56 #define CONFIG_NET_MULTI        1
  57 #undef  CONFIG_HAS_ETH1
  58
  59 #define CONFIG_MII              1       /* MII PHY management           */
  60 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  61 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  62 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  63
  64 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  65
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_BOOTFILESIZE
  71 #define CONFIG_BOOTP_BOOTPATH
  72 #define CONFIG_BOOTP_GATEWAY
  73 #define CONFIG_BOOTP_HOSTNAME
  74
  75
  76 /*
  77  * Command line configuration.
  78  */
  79 #include <config_cmd_default.h>
  80
  81 #define CONFIG_CMD_DHCP
  82 #define CONFIG_CMD_IRQ
  83 #define CONFIG_CMD_ELF
  84 #define CONFIG_CMD_NAND
  85 #define CONFIG_CMD_DATE
  86 #define CONFIG_CMD_I2C
  87 #define CONFIG_CMD_MII
  88 #define CONFIG_CMD_PING
  89 #define CONFIG_CMD_EEPROM
  90
  91
  92 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  93
  94 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  95 #define CFG_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address         */
  96
  97 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  98
  99 /*
 100  * Miscellaneous configurable options
 101  */
 102 #define CFG_LONGHELP                    /* undef to save memory         */
 103 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 104
 105 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 106 #ifdef  CFG_HUSH_PARSER
 107 #define CFG_PROMPT_HUSH_PS2     "> "
 108 #endif
 109
 110 #if defined(CONFIG_CMD_KGDB)
 111 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 112 #else
 113 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 114 #endif
 115 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 116 #define CFG_MAXARGS     16              /* max number of command args   */
 117 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 118
 119 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 120
 121 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 122
 123 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 124 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 125
 126 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 127 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 128 #define CFG_BASE_BAUD       691200
 129 #undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 130
 131 /* The following table includes the supported baudrates */
 132 #define CFG_BAUDRATE_TABLE      \
 133         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 134          57600, 115200, 230400, 460800, 921600 }
 135
 136 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 137 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 138
 139 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 140
 141 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 142
 143 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 144
 145 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 146
 147 /*-----------------------------------------------------------------------
 148  * NAND-FLASH stuff
 149  *-----------------------------------------------------------------------
 150  */
 151 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE }
 152 #define NAND_MAX_CHIPS          1
 153 #define CFG_MAX_NAND_DEVICE     1         /* Max number of NAND devices */
 154 #define NAND_BIG_DELAY_US       25
 155
 156 #define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 157 #define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 158 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 159 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 160
 161 #define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 162 #define CFG_NAND_QUIET          1
 163
 164 /*-----------------------------------------------------------------------
 165  * PCI stuff
 166  *-----------------------------------------------------------------------
 167  */
 168 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 169 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 170 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 171
 172 #define CONFIG_PCI                      /* include pci support          */
 173 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 174 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 175                                         /* resource configuration       */
 176
 177 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 178
 179 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 180 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 181 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 182 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 183 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 184 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 185 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 186 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 187 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 188
 189 /*-----------------------------------------------------------------------
 190  * Start addresses for the final memory configuration
 191  * (Set up by the startup code)
 192  * Please note that CFG_SDRAM_BASE _must_ start at 0
 193  */
 194 #define CFG_SDRAM_BASE          0x00000000
 195 #define CFG_FLASH_BASE          0xFFFC0000
 196 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 197 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 198 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
 199
 200 /*
 201  * For booting Linux, the board info and command line data
 202  * have to be in the first 8 MB of memory, since this is
 203  * the maximum mapped by the Linux kernel during initialization.
 204  */
 205 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 206 /*-----------------------------------------------------------------------
 207  * FLASH organization
 208  */
 209 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 210 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 211
 212 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 213 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 214
 215 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 216 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 217 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 218 /*
 219  * The following defines are added for buggy IOP480 byte interface.
 220  * All other boards should use the standard values (CPCI405 etc.)
 221  */
 222 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 223 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 224 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 225
 226 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 227
 228 #if 0 /* test-only */
 229 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 230 #define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 231 #endif
 232
 233 /*-----------------------------------------------------------------------
 234  * Environment Variable setup
 235  */
 236 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 237 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 238 #define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 239                                    /* total size of a CAT24WC16 is 2048 bytes */
 240
 241 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 242 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 243
 244 /*-----------------------------------------------------------------------
 245  * I2C EEPROM (CAT24WC16) for environment
 246  */
 247 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 248 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 249 #define CFG_I2C_SLAVE           0x7F
 250
 251 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 252 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 253 /* mask of address bits that overflow into the "EEPROM chip address"    */
 254 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 255 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 256                                         /* 16 byte page write mode using*/
 257                                         /* last 4 bits of the address   */
 258 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 259 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 260
 261 /*
 262  * Init Memory Controller:
 263  *
 264  * BR0/1 and OR0/1 (FLASH)
 265  */
 266
 267 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 268
 269 /*-----------------------------------------------------------------------
 270  * External Bus Controller (EBC) Setup
 271  */
 272
 273 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 274 #define CFG_EBC_PB0AP           0x92015480
 275 /*#define CFG_EBC_PB0AP           0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 276 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 277
 278 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 279 #define CFG_EBC_PB1AP           0x92015480
 280 #define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 281
 282 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 283 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 284 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 285
 286 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 287 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 288 #define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 289
 290 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 291 #define DUART0_BA       0xF0000400          /* DUART Base Address               */
 292 #define DUART1_BA       0xF0000408          /* DUART Base Address               */
 293 #define DUART2_BA       0xF0000410          /* DUART Base Address               */
 294 #define DUART3_BA       0xF0000418          /* DUART Base Address               */
 295 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 296 #define CFG_NAND_BASE   0xF4000000
 297
 298 /*-----------------------------------------------------------------------
 299  * FPGA stuff
 300  */
 301 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 302 #define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
 303
 304 /* FPGA program pin configuration */
 305 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 306 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 307 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 308 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 309 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 310
 311 /*-----------------------------------------------------------------------
 312  * Definitions for initial stack pointer and data area (in data cache)
 313  */
 314 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 315 #define CFG_TEMP_STACK_OCM        1
 316
 317 /* On Chip Memory location */
 318 #define CFG_OCM_DATA_ADDR       0xF8000000
 319 #define CFG_OCM_DATA_SIZE       0x1000
 320 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 321 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 322
 323 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 324 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 325 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 326
 327 /*-----------------------------------------------------------------------
 328  * Definitions for GPIO setup (PPC405EP specific)
 329  *
 330  * GPIO0[0]     - External Bus Controller BLAST output
 331  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 332  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 333  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 334  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 335  * GPIO0[24-27] - UART0 control signal inputs/outputs
 336  * GPIO0[28-29] - UART1 data signal input/output
 337  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 338  */
 339 #define CFG_GPIO0_OSRH          0x40000550
 340 #define CFG_GPIO0_OSRL          0x00000110
 341 #define CFG_GPIO0_ISR1H         0x00000000
 342 #define CFG_GPIO0_ISR1L         0x15555445
 343 #define CFG_GPIO0_TSRH          0x00000000
 344 #define CFG_GPIO0_TSRL          0x00000000
 345 #define CFG_GPIO0_TCR           0xF7FE0014
 346
 347 #define CFG_DUART_RST           (0x80000000 >> 14)
 348
 349 /*
 350  * Internal Definitions
 351  *
 352  * Boot Flags
 353  */
 354 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 355 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 356
 357 /*
 358  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 359  * This value will be set if iic boot eprom is disabled.
 360  */
 361 #if 0
 362 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 363 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 364 #endif
 365 #if 1
 366 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 367 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 368 #endif
 369 #if 0
 370 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 371 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 372 #endif
 373
 374 #endif  /* __CONFIG_H */