drivers/rtc/x1205.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * based on a the Linux rtc-x1207.c driver which is:
   6  *      Copyright 2004 Karen Spearel
   7  *      Copyright 2005 Alessandro Zummo
   8  *
   9  * Information and datasheet:
  10  * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 /*
  32  * Date & Time support for Xicor/Intersil X1205 RTC
  33  */
  34
  35 /* #define      DEBUG   */
  36
  37 #include <common.h>
  38 #include <command.h>
  39 #include <rtc.h>
  40 #include <i2c.h>
  41 #include <bcd.h>
  42
  43 #if defined(CONFIG_RTC_X1205) && defined(CONFIG_CMD_DATE)
  44
  45 #define CCR_SEC                 0
  46 #define CCR_MIN                 1
  47 #define CCR_HOUR                2
  48 #define CCR_MDAY                3
  49 #define CCR_MONTH               4
  50 #define CCR_YEAR                5
  51 #define CCR_WDAY                6
  52 #define CCR_Y2K                 7
  53
  54 #define X1205_REG_SR            0x3F    /* status register */
  55 #define X1205_REG_Y2K           0x37
  56 #define X1205_REG_DW            0x36
  57 #define X1205_REG_YR            0x35
  58 #define X1205_REG_MO            0x34
  59 #define X1205_REG_DT            0x33
  60 #define X1205_REG_HR            0x32
  61 #define X1205_REG_MN            0x31
  62 #define X1205_REG_SC            0x30
  63 #define X1205_REG_DTR           0x13
  64 #define X1205_REG_ATR           0x12
  65 #define X1205_REG_INT           0x11
  66 #define X1205_REG_0             0x10
  67 #define X1205_REG_Y2K1          0x0F
  68 #define X1205_REG_DWA1          0x0E
  69 #define X1205_REG_YRA1          0x0D
  70 #define X1205_REG_MOA1          0x0C
  71 #define X1205_REG_DTA1          0x0B
  72 #define X1205_REG_HRA1          0x0A
  73 #define X1205_REG_MNA1          0x09
  74 #define X1205_REG_SCA1          0x08
  75 #define X1205_REG_Y2K0          0x07
  76 #define X1205_REG_DWA0          0x06
  77 #define X1205_REG_YRA0          0x05
  78 #define X1205_REG_MOA0          0x04
  79 #define X1205_REG_DTA0          0x03
  80 #define X1205_REG_HRA0          0x02
  81 #define X1205_REG_MNA0          0x01
  82 #define X1205_REG_SCA0          0x00
  83
  84 #define X1205_CCR_BASE          0x30    /* Base address of CCR */
  85 #define X1205_ALM0_BASE         0x00    /* Base address of ALARM0 */
  86
  87 #define X1205_SR_RTCF           0x01    /* Clock failure */
  88 #define X1205_SR_WEL            0x02    /* Write Enable Latch */
  89 #define X1205_SR_RWEL           0x04    /* Register Write Enable */
  90
  91 #define X1205_DTR_DTR0          0x01
  92 #define X1205_DTR_DTR1          0x02
  93 #define X1205_DTR_DTR2          0x04
  94
  95 #define X1205_HR_MIL            0x80    /* Set in ccr.hour for 24 hr mode */
  96
  97 static void rtc_write(int reg, u8 val)
  98 {
  99         i2c_write(CFG_I2C_RTC_ADDR, reg, 2, &val, 1);
 100 }
 101
 102 /*
 103  * In the routines that deal directly with the x1205 hardware, we use
 104  * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 105  * Epoch is initialized as 2000. Time is set to UTC.
 106  */
 107 int rtc_get(struct rtc_time *tm)
 108 {
 109         u8 buf[8];
 110
 111         i2c_read(CFG_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
 112
 113         debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
 114               "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
 115               __FUNCTION__,
 116               buf[0], buf[1], buf[2], buf[3],
 117               buf[4], buf[5], buf[6], buf[7]);
 118
 119         tm->tm_sec = BCD2BIN(buf[CCR_SEC]);
 120         tm->tm_min = BCD2BIN(buf[CCR_MIN]);
 121         tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
 122         tm->tm_mday = BCD2BIN(buf[CCR_MDAY]);
 123         tm->tm_mon = BCD2BIN(buf[CCR_MONTH]); /* mon is 0-11 */
 124         tm->tm_year = BCD2BIN(buf[CCR_YEAR])
 125                 + (BCD2BIN(buf[CCR_Y2K]) * 100);
 126         tm->tm_wday = buf[CCR_WDAY];
 127
 128         debug("%s: tm is secs=%d, mins=%d, hours=%d, "
 129               "mday=%d, mon=%d, year=%d, wday=%d\n",
 130               __FUNCTION__,
 131               tm->tm_sec, tm->tm_min, tm->tm_hour,
 132               tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
 133
 134         return 0;
 135 }
 136
 137 void rtc_set(struct rtc_time *tm)
 138 {
 139         int i;
 140         u8 buf[8];
 141
 142         debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
 143               tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
 144               tm->tm_hour, tm->tm_min, tm->tm_sec);
 145
 146         buf[CCR_SEC] = BIN2BCD(tm->tm_sec);
 147         buf[CCR_MIN] = BIN2BCD(tm->tm_min);
 148
 149         /* set hour and 24hr bit */
 150         buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL;
 151
 152         buf[CCR_MDAY] = BIN2BCD(tm->tm_mday);
 153
 154         /* month, 1 - 12 */
 155         buf[CCR_MONTH] = BIN2BCD(tm->tm_mon);
 156
 157         /* year, since the rtc epoch*/
 158         buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100);
 159         buf[CCR_WDAY] = tm->tm_wday & 0x07;
 160         buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100);
 161
 162         /* this sequence is required to unlock the chip */
 163         rtc_write(X1205_REG_SR, X1205_SR_WEL);
 164         rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
 165
 166         /* write register's data */
 167         for (i = 0; i < 8; i++)
 168                 rtc_write(X1205_CCR_BASE + i, buf[i]);
 169
 170         rtc_write(X1205_REG_SR, 0);
 171 }
 172
 173 void rtc_reset(void)
 174 {
 175         /*
 176          * Nothing to do
 177          */
 178 }
 179
 180 #endif