cpu/arm926ejs/at91sam9/timer.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop <at> leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/hardware.h>
  27 #include <asm/arch/at91_pit.h>
  28 #include <asm/arch/at91_pmc.h>
  29 #include <asm/arch/at91_rstc.h>
  30 #include <asm/arch/io.h>
  31
  32 /*
  33  * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  34  * setting the 20 bit counter period to its maximum (0xfffff).
  35  */
  36 #define TIMER_LOAD_VAL  0xfffff
  37 #define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
  38 #define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
  39 #define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
  40 #define TICKS_TO_USEC(ticks) ((ticks) / 6)
  41
  42 ulong get_timer_masked(void);
  43 ulong resettime;
  44
  45 /* nothing really to do with interrupts, just starts up a counter. */
  46 int timer_init(void)
  47 {
  48         /*
  49          * Enable PITC Clock
  50          * The clock is already enabled for system controller in boot
  51          */
  52         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  53
  54         /* Enable PITC */
  55         at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
  56
  57         reset_timer_masked();
  58
  59         return 0;
  60 }
  61
  62 /*
  63  * timer without interrupts
  64  */
  65
  66 static inline ulong get_timer_raw(void)
  67 {
  68         ulong now = READ_TIMER;
  69
  70         if (now >= resettime)
  71                 return now - resettime;
  72         else
  73                 return 0xFFFFFFFFUL - (resettime - now) ;
  74 }
  75
  76 void reset_timer_masked(void)
  77 {
  78         resettime = READ_TIMER;
  79 }
  80
  81 ulong get_timer_masked(void)
  82 {
  83         return TICKS_TO_USEC(get_timer_raw());
  84
  85 }
  86
  87 void udelay_masked(unsigned long usec)
  88 {
  89         ulong tmp;
  90
  91         tmp = get_timer(0);
  92         while (get_timer(tmp) < usec)   /* our timer works in usecs */
  93                 ; /* NOP */
  94 }
  95
  96 void reset_timer(void)
  97 {
  98         reset_timer_masked();
  99 }
 100
 101 ulong get_timer(ulong base)
 102 {
 103         ulong now = get_timer_masked();
 104
 105         if (now >= base)
 106                 return now - base;
 107         else
 108                 return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ;
 109 }
 110
 111 void udelay(unsigned long usec)
 112 {
 113         udelay_masked(usec);
 114 }
 115
 116 /*
 117  * This function is derived from PowerPC code (read timebase as long long).
 118  * On ARM it just returns the timer value.
 119  */
 120 unsigned long long get_ticks(void)
 121 {
 122         return get_timer(0);
 123 }
 124
 125 /*
 126  * This function is derived from PowerPC code (timebase clock frequency).
 127  * On ARM it returns the number of timer ticks per second.
 128  */
 129 ulong get_tbclk(void)
 130 {
 131         ulong tbclk;
 132
 133         tbclk = CFG_HZ;
 134         return tbclk;
 135 }
 136
 137 /*
 138  * Reset the cpu by setting up the watchdog timer and let him time out.
 139  */
 140 void reset_cpu(ulong ignored)
 141 {
 142         /* this is the way Linux does it */
 143         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
 144                                      AT91_RSTC_PROCRST |
 145                                      AT91_RSTC_PERRST);
 146
 147         while (1);
 148         /* Never reached */
 149 }