post/lib_ppc/three.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  * Ternary instructions         instr rD,rA,rB
  29  *
  30  * Arithmetic instructions:     add, addc, adde, subf, subfc, subfe,
  31  *                              mullw, mulhw, mulhwu, divw, divwu
  32  *
  33  * The test contains a pre-built table of instructions, operands and
  34  * expected results. For each table entry, the test will cyclically use
  35  * different sets of operand registers and result registers.
  36  */
  37
  38 #ifdef CONFIG_POST
  39
  40 #include <post.h>
  41 #include "cpu_asm.h"
  42
  43 #if CONFIG_POST & CFG_POST_CPU
  44
  45 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  46     ulong op2);
  47 extern ulong cpu_post_makecr (long v);
  48
  49 static struct cpu_post_three_s
  50 {
  51     ulong cmd;
  52     ulong op1;
  53     ulong op2;
  54     ulong res;
  55 } cpu_post_three_table[] =
  56 {
  57     {
  58         OP_ADD,
  59         100,
  60         200,
  61         300
  62     },
  63     {
  64         OP_ADD,
  65         100,
  66         -200,
  67         -100
  68     },
  69     {
  70         OP_ADDC,
  71         100,
  72         200,
  73         300
  74     },
  75     {
  76         OP_ADDC,
  77         100,
  78         -200,
  79         -100
  80     },
  81     {
  82         OP_ADDE,
  83         100,
  84         200,
  85         300
  86     },
  87     {
  88         OP_ADDE,
  89         100,
  90         -200,
  91         -100
  92     },
  93     {
  94         OP_SUBF,
  95         100,
  96         200,
  97         100
  98     },
  99     {
 100         OP_SUBF,
 101         300,
 102         200,
 103         -100
 104     },
 105     {
 106         OP_SUBFC,
 107         100,
 108         200,
 109         100
 110     },
 111     {
 112         OP_SUBFC,
 113         300,
 114         200,
 115         -100
 116     },
 117     {
 118         OP_SUBFE,
 119         100,
 120         200,
 121         200 + ~100
 122     },
 123     {
 124         OP_SUBFE,
 125         300,
 126         200,
 127         200 + ~300
 128     },
 129     {
 130         OP_MULLW,
 131         200,
 132         300,
 133         200 * 300
 134     },
 135     {
 136         OP_MULHW,
 137         0x10000000,
 138         0x10000000,
 139         0x1000000
 140     },
 141     {
 142         OP_MULHWU,
 143         0x80000000,
 144         0x80000000,
 145         0x40000000
 146     },
 147     {
 148         OP_DIVW,
 149         -20,
 150         5,
 151         -4
 152     },
 153     {
 154         OP_DIVWU,
 155         0x8000,
 156         0x200,
 157         0x40
 158     },
 159 };
 160 static unsigned int cpu_post_three_size =
 161     sizeof (cpu_post_three_table) / sizeof (struct cpu_post_three_s);
 162
 163 int cpu_post_test_three (void)
 164 {
 165     int ret = 0;
 166     unsigned int i, reg;
 167     int flag = disable_interrupts();
 168
 169     for (i = 0; i < cpu_post_three_size && ret == 0; i++)
 170     {
 171         struct cpu_post_three_s *test = cpu_post_three_table + i;
 172
 173         for (reg = 0; reg < 32 && ret == 0; reg++)
 174         {
 175             unsigned int reg0 = (reg + 0) % 32;
 176             unsigned int reg1 = (reg + 1) % 32;
 177             unsigned int reg2 = (reg + 2) % 32;
 178             unsigned int stk = reg < 16 ? 31 : 15;
 179             unsigned long code[] =
 180             {
 181                 ASM_STW(stk, 1, -4),
 182                 ASM_ADDI(stk, 1, -24),
 183                 ASM_STW(3, stk, 12),
 184                 ASM_STW(4, stk, 16),
 185                 ASM_STW(reg0, stk, 8),
 186                 ASM_STW(reg1, stk, 4),
 187                 ASM_STW(reg2, stk, 0),
 188                 ASM_LWZ(reg1, stk, 12),
 189                 ASM_LWZ(reg0, stk, 16),
 190                 ASM_12(test->cmd, reg2, reg1, reg0),
 191                 ASM_STW(reg2, stk, 12),
 192                 ASM_LWZ(reg2, stk, 0),
 193                 ASM_LWZ(reg1, stk, 4),
 194                 ASM_LWZ(reg0, stk, 8),
 195                 ASM_LWZ(3, stk, 12),
 196                 ASM_ADDI(1, stk, 24),
 197                 ASM_LWZ(stk, 1, -4),
 198                 ASM_BLR,
 199             };
 200             unsigned long codecr[] =
 201             {
 202                 ASM_STW(stk, 1, -4),
 203                 ASM_ADDI(stk, 1, -24),
 204                 ASM_STW(3, stk, 12),
 205                 ASM_STW(4, stk, 16),
 206                 ASM_STW(reg0, stk, 8),
 207                 ASM_STW(reg1, stk, 4),
 208                 ASM_STW(reg2, stk, 0),
 209                 ASM_LWZ(reg1, stk, 12),
 210                 ASM_LWZ(reg0, stk, 16),
 211                 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C,
 212                 ASM_STW(reg2, stk, 12),
 213                 ASM_LWZ(reg2, stk, 0),
 214                 ASM_LWZ(reg1, stk, 4),
 215                 ASM_LWZ(reg0, stk, 8),
 216                 ASM_LWZ(3, stk, 12),
 217                 ASM_ADDI(1, stk, 24),
 218                 ASM_LWZ(stk, 1, -4),
 219                 ASM_BLR,
 220             };
 221             ulong res;
 222             ulong cr;
 223
 224             if (ret == 0)
 225             {
 226                 cr = 0;
 227                 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 228
 229                 ret = res == test->res && cr == 0 ? 0 : -1;
 230
 231                 if (ret != 0)
 232                 {
 233                     post_log ("Error at three test %d !\n", i);
 234                 }
 235             }
 236
 237             if (ret == 0)
 238             {
 239                 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 240
 241                 ret = res == test->res &&
 242                       (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 243
 244                 if (ret != 0)
 245                 {
 246                     post_log ("Error at three test %d !\n", i);
 247                 }
 248             }
 249         }
 250     }
 251
 252     if (flag)
 253         enable_interrupts();
 254
 255     return ret;
 256 }
 257
 258 #endif
 259 #endif