include/configs/taihu.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2005-2007
   6  * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30
  31 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  32 #define CONFIG_4xx              1       /*  member of PPC4xx family */
  33 #define CONFIG_TAIHU            1       /*  on a taihu board */
  34
  35 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f */
  36
  37 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  38
  39 #define CONFIG_NO_SERIAL_EEPROM
  40
  41 /*----------------------------------------------------------------------------*/
  42 #ifdef CONFIG_NO_SERIAL_EEPROM
  43
  44 /*
  45 !-------------------------------------------------------------------------------
  46 ! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
  47 ! assuming a 33MHz input clock to the 405EP from the C9531.
  48 !-------------------------------------------------------------------------------
  49 */
  50 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
  51                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
  52                               PLL_MALDIV_1 | PLL_PCIDIV_3)
  53 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
  54                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
  55                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  56 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
  57                                PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
  58                                PLL_MALDIV_1 | PLL_PCIDIV_1)
  59 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
  60                                PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
  61                                PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  62
  63 #define PLLMR0_DEFAULT          PLLMR0_333_111_55_37
  64 #define PLLMR1_DEFAULT          PLLMR1_333_111_55_37
  65 #define PLLMR0_DEFAULT_PCI66    PLLMR0_333_111_55_111
  66 #define PLLMR1_DEFAULT_PCI66    PLLMR1_333_111_55_111
  67
  68 #endif
  69 /*----------------------------------------------------------------------------*/
  70
  71 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars */
  72
  73 #define CONFIG_ENV_OVERWRITE 1
  74 #define CONFIG_PREBOOT  "echo;" \
  75         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  76         "echo"
  77
  78 #undef  CONFIG_BOOTARGS
  79 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  80         "bootfile=/tftpboot/taihu/uImage\0"                             \
  81         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
  82         "netdev=eth0\0"                                                 \
  83         "hostname=taihu\0"                                              \
  84         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  85                 "nfsroot=${serverip}:${rootpath}\0"                     \
  86         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  87         "addip=setenv bootargs ${bootargs} "                            \
  88                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  89                 ":${hostname}:${netdev}:off panic=1\0"                  \
  90         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  91         "flash_nfs=run nfsargs addip addtty;"                           \
  92                 "bootm ${kernel_addr}\0"                                \
  93         "flash_self=run ramargs addip addtty;"                          \
  94                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  95         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
  96                 "bootm\0"                                               \
  97         "kernel_addr=FC000000\0"                                        \
  98         "ramdisk_addr=FC180000\0"                                       \
  99         "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0"                 \
 100         "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;"   \
 101                 "cp.b 200000 FFFC0000 40000\0"                          \
 102         "upd=run load update\0"                                         \
 103         ""
 104 #define CONFIG_BOOTCOMMAND      "run flash_self"
 105
 106 #if 0
 107 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 108 #else
 109 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 110 #endif
 111
 112 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 113 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 114
 115 #define CONFIG_MII              1       /* MII PHY management           */
 116 #define CONFIG_PHY_ADDR         0x14    /* PHY address                  */
 117 #define CONFIG_HAS_ETH1
 118 #define CONFIG_PHY1_ADDR        0x10    /* EMAC1 PHY address            */
 119 #define CONFIG_NET_MULTI        1
 120 #define CFG_RX_ETH_BUFFER       16      /* Number of ethernet rx buffers & descriptors */
 121 #define CONFIG_PHY_RESET        1
 122
 123 /*
 124  * BOOTP options
 125  */
 126 #define CONFIG_BOOTP_BOOTFILESIZE
 127 #define CONFIG_BOOTP_BOOTPATH
 128 #define CONFIG_BOOTP_GATEWAY
 129 #define CONFIG_BOOTP_HOSTNAME
 130
 131 /*
 132  * Command line configuration.
 133  */
 134 #include <config_cmd_default.h>
 135
 136 #define CONFIG_CMD_ASKENV
 137 #define CONFIG_CMD_CACHE
 138 #define CONFIG_CMD_DHCP
 139 #define CONFIG_CMD_EEPROM
 140 #define CONFIG_CMD_ELF
 141 #define CONFIG_CMD_I2C
 142 #define CONFIG_CMD_IRQ
 143 #define CONFIG_CMD_MII
 144 #define CONFIG_CMD_NET
 145 #define CONFIG_CMD_PCI
 146 #define CONFIG_CMD_PING
 147 #define CONFIG_CMD_REGINFO
 148 #define CONFIG_CMD_SDRAM
 149 #define CONFIG_CMD_SPI
 150
 151 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 152
 153 #undef CONFIG_SPD_EEPROM                /* use SPD EEPROM for setup */
 154 #define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
 155 #define CFG_SDRAM_BANKS         2
 156
 157 /*
 158  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 159  */
 160 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
 161 #define CONFIG_SDRAM_BANK1      1       /* init onboard SDRAM bank 1 */
 162
 163 /* SDRAM timings used in datasheet */
 164 #define CFG_SDRAM_CL            3       /* CAS latency */
 165 #define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
 166 #define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
 167 #define CFG_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
 168 #define CFG_SDRAM_tRFC          66      /* Auto refresh period */
 169
 170 /*
 171  * Miscellaneous configurable options
 172  */
 173 #define CFG_LONGHELP                    /* undef to save memory         */
 174 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 175 #if defined(CONFIG_CMD_KGDB)
 176 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 177 #else
 178 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 179 #endif
 180 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
 181 #define CFG_MAXARGS     16              /* max number of command args   */
 182 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 183
 184 #define CFG_MEMTEST_START  0x0400000    /* memtest works on     */
 185 #define CFG_MEMTEST_END    0x0C00000    /* 4 ... 12 MB in DRAM  */
 186
 187 /*
 188  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 189  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 190  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 191  * The Linux BASE_BAUD define should match this configuration.
 192  *    baseBaud = cpuClock/(uartDivisor*16)
 193  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 194  * set Linux BASE_BAUD to 403200.
 195  */
 196 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 197 #undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
 198 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 199 #define CFG_BASE_BAUD           691200
 200
 201 #define CONFIG_BAUDRATE         115200
 202
 203 #define CONFIG_UART1_CONSOLE    1
 204
 205 /* The following table includes the supported baudrates */
 206 #define CFG_BAUDRATE_TABLE  \
 207     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 208
 209 #define CFG_LOAD_ADDR       0x100000    /* default load address */
 210 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 211
 212 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 213
 214 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 215 #define CONFIG_LOOPW            1       /* enable loopw command         */
 216 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 217 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 218 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 219 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 220
 221 /*-----------------------------------------------------------------------
 222  * I2C stuff
 223  *-----------------------------------------------------------------------
 224  */
 225 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 226 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 227 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 228 #define CFG_I2C_SLAVE           0x7F
 229
 230 #define CFG_I2C_NOPROBES        { 0x69 } /* avoid iprobe hangup (why?) */
 231 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  6 /* 24C02 requires 5ms delay */
 232
 233 #define CFG_I2C_EEPROM_ADDR     0x50    /* I2C boot EEPROM (24C02W)     */
 234 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 235
 236 #define CONFIG_SOFT_SPI
 237 #define SPI_SCL  spi_scl
 238 #define SPI_SDA  spi_sda
 239 #define SPI_READ spi_read()
 240 #define SPI_DELAY udelay(2)
 241 #ifndef __ASSEMBLY__
 242 void spi_scl(int);
 243 void spi_sda(int);
 244 unsigned char spi_read(void);
 245 #endif
 246
 247 /* standard dtt sensor configuration */
 248 #define CONFIG_DTT_DS1775       1
 249 #define CONFIG_DTT_SENSORS      { 0 }
 250 #define CFG_I2C_DTT_ADDR        0x49
 251
 252 /*-----------------------------------------------------------------------
 253  * PCI stuff
 254  *-----------------------------------------------------------------------
 255  */
 256 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter    */
 257 #define PCI_HOST_FORCE   1              /* configure as pci host       */
 258 #define PCI_HOST_AUTO    2              /* detected via arbiter enable */
 259
 260 #define CONFIG_PCI                      /* include pci support         */
 261 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function    */
 262 #define CONFIG_PCI_PNP                  /* do pci plug-and-play        */
 263                                         /* resource configuration      */
 264 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 265
 266 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 267 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 268 #define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
 269 #define CFG_PCI_PTM1LA      0x00000000  /* point to sdram              */
 270 #define CFG_PCI_PTM1MS      0x80000001  /* 2GB, enable hard-wired to 1 */
 271 #define CFG_PCI_PTM1PCI     0x00000000  /* Host: use this pci address  */
 272 #define CFG_PCI_PTM2LA      0x00000000  /* disabled                    */
 273 #define CFG_PCI_PTM2MS      0x00000000  /* disabled                    */
 274 #define CFG_PCI_PTM2PCI     0x04000000  /* Host: use this pci address  */
 275 #define CONFIG_EEPRO100         1
 276
 277 /*-----------------------------------------------------------------------
 278  * Start addresses for the final memory configuration
 279  * (Set up by the startup code)
 280  * Please note that CFG_SDRAM_BASE _must_ start at 0
 281  */
 282 #define CFG_SDRAM_BASE          0x00000000
 283 #define CFG_FLASH_BASE          0xFFE00000
 284 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 285 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 286 #define CFG_MONITOR_BASE        (-CFG_MONITOR_LEN)
 287
 288 /*
 289  * For booting Linux, the board info and command line data
 290  * have to be in the first 8 MB of memory, since this is
 291  * the maximum mapped by the Linux kernel during initialization.
 292  */
 293 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 294
 295 /*-----------------------------------------------------------------------
 296  * FLASH organization
 297  */
 298
 299 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 300 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 301
 302 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 303 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 304
 305 #define CFG_FLASH_ADDR0         0x555
 306 #define CFG_FLASH_ADDR1         0x2aa
 307 #define CFG_FLASH_WORD_SIZE     unsigned short
 308
 309 #ifdef CFG_ENV_IS_IN_FLASH
 310 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector  */
 311 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 312 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 313
 314 /* Address and size of Redundant Environment Sector     */
 315 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 316 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 317 #endif /* CFG_ENV_IS_IN_FLASH */
 318
 319 /*-----------------------------------------------------------------------
 320  * NVRAM organization
 321  */
 322 #define CFG_NVRAM_BASE_ADDR     0xf0000000      /* NVRAM base address */
 323 #define CFG_NVRAM_SIZE          0x1ff8          /* NVRAM size */
 324
 325 #ifdef CFG_ENV_IS_IN_NVRAM
 326 #define CFG_ENV_SIZE            0x0ff8          /* Size of Environment vars */
 327 #define CFG_ENV_ADDR            \
 328         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)       /* Env*/
 329 #endif
 330
 331 /*-----------------------------------------------------------------------
 332  * PPC405 GPIO Configuration
 333  */
 334 #define CFG_4xx_GPIO_TABLE { /*                         GPIO    Alternate1              */      \
 335 {                                                                                               \
 336 /* GPIO Core 0 */                                                                               \
 337 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast    SPI CS      */      \
 338 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1   TS1E                    */      \
 339 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2   TS2E                    */      \
 340 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3   TS1O                    */      \
 341 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4   TS2O                    */      \
 342 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5   TS3                     */      \
 343 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6   TS4                     */      \
 344 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7   TS5                     */      \
 345 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8   TS6                     */      \
 346 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk                  */      \
 347 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1                  */      \
 348 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2                  */      \
 349 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3                  */      \
 350 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4                  */      \
 351 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03   SPI SCLK    */      \
 352 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04   SPI DI      */      \
 353 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05   SPI DO      */      \
 354 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0        PCI INTA    */      \
 355 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1        PCI INTB    */      \
 356 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2        PCI INTC    */      \
 357 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3        PCI INTD    */      \
 358 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4        USB         */      \
 359 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5        EBC         */      \
 360 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6        unused      */      \
 361 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD   UART1       */      \
 362 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR               */      \
 363 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI                */      \
 364 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR               */      \
 365 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx    UART0       */      \
 366 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx                */      \
 367 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0  User LED1   */      \
 368 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1  User LED2   */      \
 369 }                                                                                               \
 370 }
 371
 372 /*
 373  * Init Memory Controller:
 374  *
 375  * BR0/1 and OR0/1 (FLASH)
 376  */
 377
 378 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
 379 #define FLASH_BASE1_PRELIM  0xFC000000  /* FLASH bank #1 */
 380
 381 /*-----------------------------------------------------------------------
 382  * Definitions for initial stack pointer and data area (in data cache)
 383  */
 384 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 385 #define CFG_TEMP_STACK_OCM        1
 386
 387 /* On Chip Memory location */
 388 #define CFG_OCM_DATA_ADDR       0xF8000000
 389 #define CFG_OCM_DATA_SIZE       0x1000
 390 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 391 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 392
 393 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 394 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 395 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 396
 397 /*-----------------------------------------------------------------------
 398  * External Bus Controller (EBC) Setup
 399  */
 400
 401 /* Memory Bank 0 (Flash/SRAM) initialization */
 402 #define CFG_EBC_PB0AP           0x03815600
 403 #define CFG_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
 404
 405 /* Memory Bank 1 (NVRAM/RTC) initialization */
 406 #define CFG_EBC_PB1AP           0x05815600
 407 #define CFG_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
 408
 409 /* Memory Bank 2 (USB device) initialization */
 410 #define CFG_EBC_PB2AP           0x03016600
 411 #define CFG_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
 412
 413 /* Memory Bank 3 (LCM and D-flip-flop) initialization */
 414 #define CFG_EBC_PB3AP           0x158FF600
 415 #define CFG_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
 416
 417 /* Memory Bank 4 (not install) initialization */
 418 #define CFG_EBC_PB4AP           0x158FF600
 419 #define CFG_EBC_PB4CR           0x5021A000
 420
 421 #define CPLD_REG0_ADDR  0x50100000
 422 #define CPLD_REG1_ADDR  0x50100001
 423 /*
 424  * Internal Definitions
 425  *
 426  * Boot Flags
 427  */
 428 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 429 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 430
 431 #if defined(CONFIG_CMD_KGDB)
 432 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 433 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 434 #endif
 435
 436 #endif  /* __CONFIG_H */