include/configs/pcu_e.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Workaround for layout bug on prototype board
  33  */
  34 #define PCU_E_WITH_SWAPPED_CS   1
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40
  41 #define CONFIG_MPC860           1       /* This is a MPC860T CPU        */
  42 #define CONFIG_MPC860T          1
  43 #define CONFIG_PCU_E            1       /* ...on a PCU E board          */
  44
  45 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  46
  47 #define CONFIG_BAUDRATE         9600
  48 #if 0
  49 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  50 #else
  51 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52 #endif
  53
  54 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  55
  56 #undef  CONFIG_BOOTARGS
  57 #define CONFIG_BOOTCOMMAND                                                      \
  58         "bootp;"                                                                \
  59         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  60         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  61         "bootm"
  62
  63 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  64 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  65
  66 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  67
  68 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  69
  70 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
  71
  72 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  73
  74 #define CONFIG_SPI                      /* enable SPI driver            */
  75 #define CONFIG_SPI_X                    /* 16 bit EEPROM addressing     */
  76
  77 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
  78 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  79 #define CFG_I2C_SLAVE           0x7F
  80
  81
  82 /* ----------------------------------------------------------------
  83  * Offset to initial SPI buffers in DPRAM (used if the environment
  84  * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
  85  * use at an early stage. It is used between the two initialization
  86  * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
  87  * far enough from the start of the data area (as well as from the
  88  * stack pointer).
  89  * ---------------------------------------------------------------- */
  90 #define CFG_SPI_INIT_OFFSET             0xB00
  91
  92
  93 /*
  94  * Command line configuration.
  95  */
  96 #include <config_cmd_default.h>
  97 #define CONFIG_CMD_BSP
  98 #define CONFIG_CMD_DATE
  99 #define CONFIG_CMD_DHCP
 100 #define CONFIG_CMD_EEPROM
 101 #define CONFIG_CMD_NFS
 102 #define CONFIG_CMD_SNTP
 103
 104
 105 /*
 106  * BOOTP options
 107  */
 108 #define CONFIG_BOOTP_SUBNETMASK
 109 #define CONFIG_BOOTP_HOSTNAME
 110 #define CONFIG_BOOTP_BOOTPATH
 111 #define CONFIG_BOOTP_BOOTFILESIZE
 112
 113
 114 /*
 115  * Miscellaneous configurable options
 116  */
 117 #define CFG_LONGHELP                    /* undef to save memory         */
 118 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 119 #if defined(CONFIG_CMD_KGDB)
 120 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 121 #else
 122 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 123 #endif
 124 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 125 #define CFG_MAXARGS     16              /* max number of command args   */
 126 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 127
 128 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 129 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
 130
 131 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 132
 133 #define CFG_PIO_MODE            0       /* IDE interface in PIO Mode 0  */
 134
 135 /* Ethernet hardware configuration done using port pins */
 136 #define CFG_PB_ETH_RESET        0x00000020              /* PB 26        */
 137 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 138 #define CFG_PA_ETH_MDDIS        0x4000                  /* PA  1        */
 139 #define CFG_PB_ETH_POWERDOWN    0x00000800              /* PB 20        */
 140 #define CFG_PB_ETH_CFG1         0x00000400              /* PB 21        */
 141 #define CFG_PB_ETH_CFG2         0x00000200              /* PB 22        */
 142 #define CFG_PB_ETH_CFG3         0x00000100              /* PB 23        */
 143 #else /* XXX */
 144 #define CFG_PB_ETH_MDDIS        0x00000010              /* PB 27        */
 145 #define CFG_PB_ETH_POWERDOWN    0x00000100              /* PB 23        */
 146 #define CFG_PB_ETH_CFG1         0x00000200              /* PB 22        */
 147 #define CFG_PB_ETH_CFG2         0x00000400              /* PB 21        */
 148 #define CFG_PB_ETH_CFG3         0x00000800              /* PB 20        */
 149 #endif /* XXX */
 150
 151 /* Ethernet settings:
 152  * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
 153  */
 154 #define CFG_ETH_MDDIS_VALUE     0
 155 #define CFG_ETH_CFG1_VALUE      1
 156 #define CFG_ETH_CFG2_VALUE      1
 157 #define CFG_ETH_CFG3_VALUE      1
 158
 159 /* PUMA configuration */
 160 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 161 #define CFG_PB_PUMA_PROG        0x00000010              /* PB 27        */
 162 #else /* XXX */
 163 #define CFG_PA_PUMA_PROG        0x4000                  /* PA  1        */
 164 #endif /* XXX */
 165 #define CFG_PC_PUMA_DONE        0x0008                  /* PC 12        */
 166 #define CFG_PC_PUMA_INIT        0x0004                  /* PC 13        */
 167
 168 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 169
 170 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 171
 172 /*
 173  * Low Level Configuration Settings
 174  * (address mappings, register initial values, etc.)
 175  * You should know what you are doing if you make changes here.
 176  */
 177 /*-----------------------------------------------------------------------
 178  * Internal Memory Mapped Register
 179  */
 180 #define CFG_IMMR                0xFE000000
 181
 182 /*-----------------------------------------------------------------------
 183  * Definitions for initial stack pointer and data area (in DPRAM)
 184  */
 185 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 186 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 187 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 188 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 189 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 190
 191 /*-----------------------------------------------------------------------
 192  * Address accessed to reset the board - must not be mapped/assigned
 193  */
 194 #define CFG_RESET_ADDRESS       0xFEFFFFFF
 195
 196 /*-----------------------------------------------------------------------
 197  * Start addresses for the final memory configuration
 198  * (Set up by the startup code)
 199  * Please note that CFG_SDRAM_BASE _must_ start at 0
 200  */
 201 #define CFG_SDRAM_BASE          0x00000000
 202 /* this is an ugly hack needed because of the silly non-constant address map */
 203 #define CFG_FLASH_BASE          (0-flash_info[0].size-flash_info[1].size)
 204
 205 #if defined(DEBUG)
 206 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 207 #else
 208 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 209 #endif
 210 #define CFG_MONITOR_BASE        TEXT_BASE
 211 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 212
 213 /*
 214  * For booting Linux, the board info and command line data
 215  * have to be in the first 8 MB of memory, since this is
 216  * the maximum mapped by the Linux kernel during initialization.
 217  */
 218 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 219 /*-----------------------------------------------------------------------
 220  * FLASH organization
 221  */
 222 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 223 #define CFG_MAX_FLASH_SECT      160     /* max number of sectors on one chip    */
 224
 225 #define CFG_FLASH_ERASE_TOUT    180000  /* Timeout for Flash Erase (in ms)      */
 226 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 227
 228 #if 0
 229 /* Start port with environment in flash; switch to SPI EEPROM later */
 230 #define CFG_ENV_IS_IN_FLASH     1
 231 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment            */
 232 #define CFG_ENV_ADDR        0xFFFFE000  /* Address    of Environment Sector     */
 233 #define CFG_ENV_SECT_SIZE       0x2000  /* use the top-most 8k boot sector      */
 234 #define CFG_ENV_IS_EMBEDDED     1       /* short-cut compile-time test          */
 235 #else
 236 /* Final version: environment in EEPROM */
 237 #define CFG_ENV_IS_IN_EEPROM    1
 238 #define CFG_I2C_EEPROM_ADDR     0
 239 #define CFG_I2C_EEPROM_ADDR_LEN 2
 240 #define CFG_ENV_OFFSET          1024
 241 #define CFG_ENV_SIZE            1024
 242 #endif
 243
 244 /*-----------------------------------------------------------------------
 245  * Cache Configuration
 246  */
 247 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 248 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 249
 250 /*-----------------------------------------------------------------------
 251  * SYPCR - System Protection Control                            11-9
 252  * SYPCR can only be written once after reset!
 253  *-----------------------------------------------------------------------
 254  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 255  */
 256 #if defined(CONFIG_WATCHDOG)
 257 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 258                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 259 #else
 260 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 261 #endif
 262
 263 /*-----------------------------------------------------------------------
 264  * SIUMCR - SIU Module Configuration                            11-6
 265  *-----------------------------------------------------------------------
 266  * External Arbitration max. priority (7),
 267  * Debug pins configuration '11',
 268  * Asynchronous external master enable.
 269  */
 270 /* => 0x70600200 */
 271 #define CFG_SIUMCR      (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
 272
 273 /*-----------------------------------------------------------------------
 274  * TBSCR - Time Base Status and Control                         11-26
 275  *-----------------------------------------------------------------------
 276  * Clear Reference Interrupt Status, Timebase freezing enabled
 277  */
 278 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 279
 280 /*-----------------------------------------------------------------------
 281  * PISCR - Periodic Interrupt Status and Control                11-31
 282  *-----------------------------------------------------------------------
 283  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 284  */
 285 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 286
 287 /*-----------------------------------------------------------------------
 288  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 289  *-----------------------------------------------------------------------
 290  * Reset PLL lock status sticky bit, timer expired status bit and timer
 291  * interrupt status bit, set PLL multiplication factor !
 292  */
 293 /* 0x00004080 */
 294 #define CFG_PLPRCR_MF   0       /* (0+1) * 50 = 50 MHz Clock */
 295 #define CFG_PLPRCR                                                      \
 296                 (       (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |            \
 297                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 298                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 299                         PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/   \
 300                 )
 301
 302 #define CONFIG_8xx_GCLK_FREQ    ((CFG_PLPRCR_MF+1)*50000000)
 303
 304 /*-----------------------------------------------------------------------
 305  * SCCR - System Clock and reset Control Register               15-27
 306  *-----------------------------------------------------------------------
 307  * Set clock output, timebase and RTC source and divider,
 308  * power management and some other internal clocks
 309  *
 310  * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
 311  */
 312 #define SCCR_MASK       SCCR_EBDF11
 313 /* 0x01800000 */
 314 #define CFG_SCCR        (SCCR_COM00     | /*SCCR_TBS|*/         \
 315                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 316                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 317                          SCCR_EBDF00 |   SCCR_DFSYNC00 |        \
 318                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 319                          SCCR_DFNH000   |   SCCR_DFLCD100 |     \
 320                          SCCR_DFALCD01)
 321
 322 /*-----------------------------------------------------------------------
 323  * RTCSC - Real-Time Clock Status and Control Register          11-27
 324  *-----------------------------------------------------------------------
 325  *
 326  * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
 327  *
 328  * Don't expect the "date" command to work without a 32kHz clock input!
 329  */
 330 /* 0x00C3 => 0x0003 */
 331 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 332
 333
 334 /*-----------------------------------------------------------------------
 335  * RCCR - RISC Controller Configuration Register                19-4
 336  *-----------------------------------------------------------------------
 337  */
 338 #define CFG_RCCR 0x0000
 339
 340 /*-----------------------------------------------------------------------
 341  * RMDS - RISC Microcode Development Support Control Register
 342  *-----------------------------------------------------------------------
 343  */
 344 #define CFG_RMDS 0
 345
 346 /*-----------------------------------------------------------------------
 347  *
 348  * Interrupt Levels
 349  *-----------------------------------------------------------------------
 350  */
 351 #define CFG_CPM_INTERRUPT       13      /* SIU_LEVEL6   */
 352
 353 /*-----------------------------------------------------------------------
 354  *
 355  *-----------------------------------------------------------------------
 356  *
 357  */
 358 #define CFG_DER 0
 359
 360 /*
 361  * Init Memory Controller:
 362  *
 363  * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 364  */
 365
 366 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 367 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 368 #define FLASH_BASE6_PRELIM      0xFF000000      /* FLASH bank #1        */
 369 #else /* XXX */
 370 #define FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank #1        */
 371 #endif /* XXX */
 372
 373 /*
 374  * used to re-map FLASH: restrict access enough but not too much to
 375  * meddle with FLASH accesses
 376  */
 377 #define CFG_REMAP_OR_AM         0xFF800000      /* OR addr mask */
 378 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 379
 380 /* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1                  */
 381 #define CFG_OR_TIMING_FLASH     (OR_SCY_8_CLK | OR_EHTR)
 382
 383 #define CFG_OR0_REMAP   ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
 384                                 CFG_OR_TIMING_FLASH)
 385 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
 386                                 CFG_OR_TIMING_FLASH)
 387 /* 16 bit, bank valid */
 388 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 389
 390 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 391 #define CFG_OR6_REMAP   CFG_OR0_REMAP
 392 #define CFG_OR6_PRELIM  CFG_OR0_PRELIM
 393 #define CFG_BR6_PRELIM  ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 394 #else /* XXX */
 395 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 396 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 397 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 398 #endif /* XXX */
 399
 400 /*
 401  * BR2/OR2: SDRAM
 402  *
 403  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 404  */
 405 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 406 #define SDRAM_BASE5_PRELIM      0x00000000      /* SDRAM bank */
 407 #else /* XXX */
 408 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank */
 409 #endif /* XXX */
 410 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map 128 MB (>SDRAM_MAX_SIZE!) */
 411 #define SDRAM_TIMING            OR_CSNT_SAM     /* SDRAM-Timing */
 412
 413 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 414
 415 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 416 #define CFG_OR5_PRELIM  (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 417 #define CFG_BR5_PRELIM  ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 418 #else /* XXX */
 419 #define CFG_OR2_PRELIM  (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 420 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 421 #endif /* XXX */
 422
 423 /*
 424  * BR3/OR3: CAN Controller
 425  *      BR3: 0x10000401         OR3: 0xffff818a
 426  */
 427 #define CAN_CTRLR_BASE          0x10000000      /* CAN Controller */
 428 #define CAN_CTRLR_OR_AM         0xFFFF8000      /* 32 kB */
 429 #define CAN_CTRLR_TIMING        (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
 430
 431 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 432 #define CFG_BR4_PRELIM          ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 433 #define CFG_OR4_PRELIM          (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
 434 #else /* XXX */
 435 #define CFG_BR3_PRELIM          ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 436 #define CFG_OR3_PRELIM          (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
 437 #endif /* XXX */
 438
 439 /*
 440  * BR4/OR4: PUMA Config
 441  *
 442  * Memory controller will be used in 2 modes:
 443  *
 444  * - "read" mode:
 445  *      BR4: 0x10100801         OR4: 0xffff8530
 446  * - "load" mode (chip select on UPM B):
 447  *      BR4: 0x101008c1         OR4: 0xffff8630
 448  *
 449  * Default initialization is in "read" mode
 450  */
 451 #define PUMA_CONF_BASE          0x10100000      /* PUMA Config */
 452 #define PUMA_CONF_OR_AM         0xFFFF8000      /* 32 kB */
 453 #define PUMA_CONF_LOAD_TIMING   (OR_ACS_DIV2     | OR_SCY_3_CLK)
 454 #define PUMA_CONF_READ_TIMING   (OR_G5LA | OR_BI | OR_SCY_3_CLK)
 455
 456 #define PUMA_CONF_BR_LOAD       ((PUMA_CONF_BASE & BR_BA_MSK) | \
 457                                         BR_PS_16 | BR_MS_UPMB | BR_V)
 458 #define PUMA_CONF_OR_LOAD       (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
 459
 460 #define PUMA_CONF_BR_READ       ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 461 #define PUMA_CONF_OR_READ       (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
 462
 463 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 464 #define CFG_BR3_PRELIM          PUMA_CONF_BR_READ
 465 #define CFG_OR3_PRELIM          PUMA_CONF_OR_READ
 466 #else /* XXX */
 467 #define CFG_BR4_PRELIM          PUMA_CONF_BR_READ
 468 #define CFG_OR4_PRELIM          PUMA_CONF_OR_READ
 469 #endif /* XXX */
 470
 471 /*
 472  * BR5/OR5: PUMA: SMA Bus 8 Bit
 473  *      BR5: 0x10200401         OR5: 0xffe0010a
 474  */
 475 #define PUMA_SMA8_BASE          0x10200000      /* PUMA SMA Bus 8 Bit */
 476 #define PUMA_SMA8_OR_AM         0xFFE00000      /* 2 MB */
 477 #define PUMA_SMA8_TIMING        (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 478
 479 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 480 #define CFG_BR2_PRELIM          ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 481 #define CFG_OR2_PRELIM          (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 482 #else /* XXX */
 483 #define CFG_BR5_PRELIM          ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 484 #define CFG_OR5_PRELIM          (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 485 #endif /* XXX */
 486
 487 /*
 488  * BR6/OR6: PUMA: SMA Bus 16 Bit
 489  *      BR6: 0x10600801         OR6: 0xffe0010a
 490  */
 491 #define PUMA_SMA16_BASE         0x10600000      /* PUMA SMA Bus 16 Bit */
 492 #define PUMA_SMA16_OR_AM        0xFFE00000      /* 2 MB */
 493 #define PUMA_SMA16_TIMING       (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 494
 495 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 496 #define CFG_BR1_PRELIM          ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 497 #define CFG_OR1_PRELIM          (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 498 #else /* XXX */
 499 #define CFG_BR6_PRELIM          ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 500 #define CFG_OR6_PRELIM          (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 501 #endif /* XXX */
 502
 503 /*
 504  * BR7/OR7: PUMA: external Flash
 505  *      BR7: 0x10a00801         OR7: 0xfe00010a
 506  */
 507 #define PUMA_FLASH_BASE         0x10A00000      /* PUMA external Flash */
 508 #define PUMA_FLASH_OR_AM        0xFE000000      /* 32 MB */
 509 #define PUMA_FLASH_TIMING       (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 510
 511 #define CFG_BR7_PRELIM          ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 512 #define CFG_OR7_PRELIM          (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
 513
 514 /*
 515  * Memory Periodic Timer Prescaler
 516  */
 517
 518 /* periodic timer for refresh */
 519 #define CFG_MPTPR       0x0200
 520
 521 /*
 522  * MAMR settings for SDRAM
 523  * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
 524  *              MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
 525  * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
 526  */
 527 /* periodic timer for refresh */
 528 #define CFG_MAMR_PTA    0x30    /* = 48 */
 529
 530 #define CFG_MAMR        ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
 531                           MAMR_AMA_TYPE_1       | \
 532                           MAMR_G0CLA_A10        | \
 533                           MAMR_RLFA_1X          | \
 534                           MAMR_WLFA_1X          | \
 535                           MAMR_TLFA_8X          )
 536
 537 /*
 538  * Internal Definitions
 539  *
 540  * Boot Flags
 541  */
 542 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 543 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 544
 545 #endif  /* __CONFIG_H */