include/configs/BC3450.h

   1 /*
   2  * -- Version 1.1 --
   3  *
   4  * (C) Copyright 2003-2005
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * (C) Copyright 2004-2005
   8  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   9  *
  10  * (C) Copyright 2005
  11  * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12  *
  13  * History:
  14  *      1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  */
  41 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU           */
  42 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU)   */
  43 #define CONFIG_TQM5200          1       /* ... on a TQM5200 module          */
  44
  45 #define CONFIG_BC3450           1       /* ... on a BC3450 mainboard        */
  46 #define CONFIG_BC3450_PS2       1       /*  + a PS/2 converter onboard      */
  47 #define CONFIG_BC3450_IDE       1       /*  + IDE drives (Compact Flash)    */
  48 #define CONFIG_BC3450_USB       1       /*  + USB support                   */
  49 # define CONFIG_FAT             1       /*    + FAT support                 */
  50 # define CONFIG_EXT2            1       /*    + EXT2 support                */
  51 #undef CONFIG_BC3450_BUZZER             /*  + Buzzer onboard                */
  52 #undef CONFIG_BC3450_CAN                /*  + CAN transceiver               */
  53 #undef CONFIG_BC3450_DS1340             /*  + a RTC DS1340 onboard          */
  54 #undef CONFIG_BC3450_DS3231             /*  + a RTC DS3231 onboard      tbd */
  55 #undef CONFIG_BC3450_AC97               /*  + AC97 on PSC2,             tbd */
  56 #define CONFIG_BC3450_FP        1       /*  + enable FP O/P                 */
  57 #undef CONFIG_BC3450_CRT                /*  + enable CRT O/P (Debug only!)  */
  58
  59 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz     */
  60
  61 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  62 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
  63
  64 /*
  65  * Serial console configuration
  66  */
  67 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  68 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps            */
  69 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  70
  71 /*
  72  * AT-PS/2 Multiplexer
  73  */
  74 #ifdef CONFIG_BC3450_PS2
  75 # define CONFIG_PS2KBD                  /* AT-PS/2 Keyboard             */
  76 # define CONFIG_PS2MULT                 /* .. on PS/2 Multiplexer       */
  77 # define CONFIG_PS2SERIAL       6               /* .. on PSC6           */
  78 # define CONFIG_PS2MULT_DELAY   (CFG_HZ/2)      /* Initial delay        */
  79 # define CONFIG_BOARD_EARLY_INIT_R
  80 #endif /* CONFIG_BC3450_PS2 */
  81
  82 /*
  83  * PCI Mapping:
  84  * 0x40000000 - 0x4fffffff - PCI Memory
  85  * 0x50000000 - 0x50ffffff - PCI IO Space
  86  */
  87 # define CONFIG_PCI             1
  88 # define CONFIG_PCI_PNP         1
  89 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  90
  91 #define CONFIG_PCI_MEM_BUS      0x40000000
  92 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  93 #define CONFIG_PCI_MEM_SIZE     0x10000000
  94
  95 #define CONFIG_PCI_IO_BUS       0x50000000
  96 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  97 #define CONFIG_PCI_IO_SIZE      0x01000000
  98
  99 #define CONFIG_NET_MULTI        1
 100 /*#define CONFIG_EEPRO100       XXX - FIXME: conflicts when CONFIG_MII is enabled */
 101 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
 102 #define CONFIG_NS8382X          1
 103
 104 /*
 105  * Video console
 106  */
 107 # define CONFIG_VIDEO
 108 # define CONFIG_VIDEO_SM501
 109 # define CONFIG_VIDEO_SM501_32BPP
 110 # define CONFIG_CFB_CONSOLE
 111 # define CONFIG_VIDEO_LOGO
 112 # define CONFIG_VGA_AS_SINGLE_DEVICE
 113 # define CONFIG_CONSOLE_EXTRA_INFO      /* display Board/Device-Infos */
 114 # define CONFIG_VIDEO_SW_CURSOR
 115 # define CONFIG_SPLASH_SCREEN
 116 # define CFG_CONSOLE_IS_IN_ENV
 117
 118 /*
 119  * Partitions
 120  */
 121 #define CONFIG_MAC_PARTITION
 122 #define CONFIG_DOS_PARTITION
 123 #define CONFIG_ISO_PARTITION
 124
 125 /*
 126  * USB
 127  */
 128 #ifdef CONFIG_BC3450_USB
 129 # define CONFIG_USB_OHCI
 130 # define CONFIG_USB_STORAGE
 131 #endif /* CONFIG_BC3450_USB */
 132
 133 /*
 134  * POST support
 135  */
 136 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 137                                  CFG_POST_CPU      | \
 138                                  CFG_POST_I2C)
 139
 140 #ifdef CONFIG_POST
 141 /* preserve space for the post_word at end of on-chip SRAM */
 142 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 143 #endif /* CONFIG_POST */
 144
 145
 146 /*
 147  * BOOTP options
 148  */
 149 #define CONFIG_BOOTP_BOOTFILESIZE
 150 #define CONFIG_BOOTP_BOOTPATH
 151 #define CONFIG_BOOTP_GATEWAY
 152 #define CONFIG_BOOTP_HOSTNAME
 153
 154
 155 /*
 156  * Command line configuration.
 157  */
 158 #include <config_cmd_default.h>
 159
 160 #define CONFIG_CMD_ASKENV
 161 #define CONFIG_CMD_DATE
 162 #define CONFIG_CMD_DHCP
 163 #define CONFIG_CMD_ECHO
 164 #define CONFIG_CMD_EEPROM
 165 #define CONFIG_CMD_I2C
 166 #define CONFIG_CMD_JFFS2
 167 #define CONFIG_CMD_MII
 168 #define CONFIG_CMD_NFS
 169 #define CONFIG_CMD_PING
 170 #define CONFIG_CMD_REGINFO
 171 #define CONFIG_CMD_SNTP
 172 #define CONFIG_CMD_BSP
 173
 174 #ifdef CONFIG_VIDEO
 175     #define CONFIG_CMD_BMP
 176 #endif
 177
 178 #ifdef CONFIG_BC3450_IDE
 179     #define CONFIG_CMD_IDE
 180 #endif
 181
 182 #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
 183     #ifdef CONFIG_FAT
 184         #define CONFIG_CMD_FAT
 185     #endif
 186
 187     #ifdef CONFIG_EXT2
 188         #define CONFIG_CMD_EXT2
 189     #endif
 190 #endif
 191
 192 #ifdef CONFIG_BC3450_USB
 193     #define CONFIG_CMD_USB
 194 #endif
 195
 196 #ifdef CONFIG_PCI
 197     #define CONFIG_CMD_PCI
 198 #endif
 199
 200 #ifdef CONFIG_POST
 201     #define CONFIG_CMD_DIAG
 202 #endif
 203
 204
 205 #define CONFIG_TIMESTAMP                /* display image timestamps */
 206
 207 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 208 #   define CFG_LOWBOOT          1
 209 #endif
 210
 211 /*
 212  * Autobooting
 213  */
 214 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 215 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 216
 217 #define CONFIG_PREBOOT  "echo;" \
 218         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 219         "echo;"
 220
 221 #undef  CONFIG_BOOTARGS
 222
 223 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 224         "netdev=eth0\0"                                                 \
 225         "ipaddr=192.168.1.10\0"                                         \
 226         "serverip=192.168.1.3\0"                                        \
 227         "netmask=255.255.255.0\0"                                       \
 228         "hostname=bc3450\0"                                             \
 229         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 230         "kernel_addr=fc0a0000\0"                                        \
 231         "ramdisk_addr=fc1c0000\0"                                       \
 232         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 233         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 234                 "nfsroot=$(serverip):$(rootpath)\0"                     \
 235         "ideargs=setenv bootargs root=/dev/hda2 ro\0"                   \
 236         "addip=setenv bootargs $(bootargs) "                            \
 237                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 238                 ":$(hostname):$(netdev):off panic=1\0"                  \
 239         "addcons=setenv bootargs $(bootargs) "                          \
 240                 "console=ttyS0,$(baudrate) console=tty0\0"              \
 241         "flash_self=run ramargs addip addcons;"                         \
 242                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 243         "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
 244         "net_nfs=tftp 200000 $(bootfile); "                             \
 245                 "run nfsargs addip addcons; bootm\0"                    \
 246         "ide_nfs=run nfsargs addip addcons; "                           \
 247                 "disk 200000 0:1; bootm\0"                              \
 248         "ide_ide=run ideargs addip addcons; "                           \
 249                 "disk 200000 0:1; bootm\0"                              \
 250         "usb_self=run usbload; run ramargs addip addcons; "             \
 251                 "bootm 200000 400000\0"                                 \
 252         "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
 253                 "usbboot 400000 0:2\0"                                  \
 254         "bootfile=uImage\0"                                             \
 255         "load=tftp 200000 $(u-boot)\0"                                  \
 256         "u-boot=u-boot.bin\0"                                           \
 257         "update=protect off FC000000 FC05FFFF;"                         \
 258                 "erase FC000000 FC05FFFF;"                              \
 259                 "cp.b 200000 FC000000 $(filesize);"                     \
 260                 "protect on FC000000 FC05FFFF\0"                        \
 261         ""
 262
 263 #define CONFIG_BOOTCOMMAND      "run flash_self"
 264
 265 /*
 266  * IPB Bus clocking configuration.
 267  */
 268 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 269
 270 /*
 271  * PCI Bus clocking configuration
 272  *
 273  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 274  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 275  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 276  */
 277 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 278 # define CFG_PCICLK_EQUALS_IPBCLK_DIV2  /* define for 66MHz speed */
 279 #endif
 280
 281 /*
 282  * I2C configuration
 283  */
 284 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 285 #define CFG_I2C_MODULE          2       /* Select I2C module #2 */
 286
 287 /*
 288  * I2C clock frequency
 289  *
 290  * Please notice, that the resulting clock frequency could differ from the
 291  * configured value. This is because the I2C clock is derived from system
 292  * clock over a frequency divider with only a few divider values. U-boot
 293  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 294  * approximation allways lies below the configured value, never above.
 295  */
 296 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 297 #define CFG_I2C_SLAVE           0x7F
 298
 299 /*
 300  * EEPROM configuration for I²C EEPROM M24C32
 301  * M24C64 should work also. For other EEPROMs config should be verified.
 302  *
 303  * The TQM5200 module may hold an EEPROM at address 0x50.
 304  */
 305 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x (TQM) */
 306 #define CFG_I2C_EEPROM_ADDR_LEN         2
 307 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 308 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 309
 310 /*
 311  * RTC configuration
 312  */
 313 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 314 # define CONFIG_RTC_M41T11      1
 315 # define CFG_I2C_RTC_ADDR       0x68
 316 #else
 317 # define CONFIG_RTC_MPC5200     1       /* use MPC5200 internal RTC */
 318 # define CONFIG_BOARD_EARLY_INIT_R
 319 #endif
 320
 321 /*
 322  * Flash configuration
 323  */
 324 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 325
 326 /* use CFI flash driver if no module variant is spezified */
 327 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 328 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 329 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 330 #define CFG_FLASH_EMPTY_INFO
 331 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 332 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 333 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 334
 335 #if !defined(CFG_LOWBOOT)
 336 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 337 #else   /* CFG_LOWBOOT */
 338 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 339 #endif  /* CFG_LOWBOOT */
 340 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 341                                            (= chip selects) */
 342 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 343 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 344
 345 /* Dynamic MTD partition support */
 346 #define CONFIG_JFFS2_CMDLINE
 347 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 348 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 349                                                 "1408k(kernel),"        \
 350                                                 "2m(initrd),"           \
 351                                                 "4m(small-fs),"         \
 352                                                 "16m(big-fs),"          \
 353                                                 "8m(misc)"
 354
 355 /*
 356  * Environment settings
 357  */
 358 #define CFG_ENV_IS_IN_FLASH     1
 359 #define CFG_ENV_SIZE            0x10000
 360 #define CFG_ENV_SECT_SIZE       0x20000
 361 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 362 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 363
 364 /*
 365  * Memory map
 366  */
 367 #define CFG_MBAR                0xF0000000
 368 #define CFG_SDRAM_BASE          0x00000000
 369 #define CFG_DEFAULT_MBAR        0x80000000
 370
 371 /* Use ON-Chip SRAM until RAM will be available */
 372 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 373 #ifdef CONFIG_POST
 374 /* preserve space for the post_word at end of on-chip SRAM */
 375 # define CFG_INIT_RAM_END       MPC5XXX_SRAM_POST_SIZE
 376 #else
 377 # define CFG_INIT_RAM_END       MPC5XXX_SRAM_SIZE
 378 #endif /*CONFIG_POST*/
 379
 380 #define CFG_GBL_DATA_SIZE       128     /* Bytes reserved for initial data  */
 381 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 382 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 383
 384 #define CFG_MONITOR_BASE        TEXT_BASE
 385 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 386 #   define CFG_RAMBOOT          1
 387 #endif
 388
 389 #define CFG_MONITOR_LEN         (384 << 10) /* Reserve 384 kB for Monitor   */
 390 #define CFG_MALLOC_LEN          (128 << 10) /* Reserve 128 kB for malloc()  */
 391 #define CFG_BOOTMAPSZ           (8 << 20)   /* Initial Memory map for Linux */
 392
 393 /*
 394  * Ethernet configuration
 395  *
 396  * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
 397  */
 398 #define CONFIG_MPC5xxx_FEC      1
 399 #undef CONFIG_FEC_10MBIT
 400 #define CONFIG_PHY_ADDR         0x00
 401
 402 /*
 403  * GPIO configuration on BC3450
 404  *
 405  *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
 406  *  PSC2:   UART2                        [0x xxxxxx4x]
 407  *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
 408  *  PSC3:   USB2                         [0x xxxxx1xx]
 409  *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
 410  *            (this has to match
 411  *            CONFIG_USB_CONFIG which is
 412  *            used by usb_ohci.c to set
 413  *            the USB ports)
 414  *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
 415  *            (this is reset to '5'
 416  *            in FEC driver: fec.c)
 417  *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
 418  *  ATA/CS: ???                          [0x x1xxxxxx]
 419  *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
 420  *  CS1:    Use Pin gpio_wkup_6 as second
 421  *          SDRAM chip select (mem_cs1)
 422  *  Timer:  CAN2 / SPI
 423  *  I2C:    CAN1 / I²C2                  [0x bxxxxxxx]
 424  */
 425 #ifdef CONFIG_BC3450_AC97
 426 # define CFG_GPS_PORT_CONFIG    0xb1502124
 427 #else /* PSC2=UART2 */
 428 # define CFG_GPS_PORT_CONFIG    0xb1502144
 429 #endif
 430
 431 /*
 432  * Miscellaneous configurable options
 433  */
 434 #define CFG_LONGHELP                            /* undef to save memory     */
 435 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt   */
 436 #if defined(CONFIG_CMD_KGDB)
 437 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size  */
 438 #else
 439 #define CFG_CBSIZE              256             /* Console I/O Buffer Size  */
 440 #endif
 441 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size  */
 442 #define CFG_MAXARGS             16              /* max no of command args   */
 443 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Arg. Buffer Size    */
 444
 445 #define CFG_ALT_MEMTEST                         /* Enable an alternative,   */
 446                                                 /*  more extensive mem test */
 447
 448 #define CFG_MEMTEST_START       0x00100000      /* memtest works on         */
 449 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM      */
 450
 451 #define CFG_LOAD_ADDR           0x100000        /* default load address     */
 452
 453 #define CFG_HZ                  1000            /* dec freq: 1ms ticks      */
 454
 455 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                 */
 456 #if defined(CONFIG_CMD_KGDB)
 457 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value    */
 458 #endif
 459
 460 /*
 461  * Enable loopw command.
 462  */
 463 #define CONFIG_LOOPW
 464
 465 /*
 466  * Various low-level settings
 467  */
 468 #if defined(CONFIG_MPC5200)
 469 # define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
 470 # define CFG_HID0_FINAL         HID0_ICE
 471 #else
 472 # define CFG_HID0_INIT          0
 473 # define CFG_HID0_FINAL         0
 474 #endif
 475
 476 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 477 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 478 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 479 # define CFG_BOOTCS_CFG         0x0008DF30      /* for pci_clk  = 66 MHz */
 480 #else
 481 # define CFG_BOOTCS_CFG         0x0004DF30      /* for pci_clk = 33 MHz  */
 482 #endif
 483 #define CFG_CS0_START           CFG_FLASH_BASE
 484 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 485
 486 /* automatic configuration of chip selects */
 487 #ifdef CONFIG_TQM5200
 488 # define CONFIG_LAST_STAGE_INIT
 489 #endif /* CONFIG_TQM5200 */
 490
 491 /*
 492  * SRAM - Do not map below 2 GB in address space, because this area is used
 493  * for SDRAM autosizing.
 494  */
 495 #ifdef CONFIG_TQM5200
 496 # define CFG_CS2_START          0xE5000000
 497 # define CFG_CS2_SIZE           0x100000        /* 1 MByte */
 498 # define CFG_CS2_CFG            0x0004D930
 499 #endif /* CONFIG_TQM5200 */
 500
 501 /*
 502  * Grafic controller - Do not map below 2 GB in address space, because this
 503  * area is used for SDRAM autosizing.
 504  */
 505 #ifdef CONFIG_TQM5200
 506 # define SM501_FB_BASE          0xE0000000
 507 # define CFG_CS1_START          (SM501_FB_BASE)
 508 # define CFG_CS1_SIZE           0x4000000       /* 64 MByte */
 509 # define CFG_CS1_CFG            0x8F48FF70
 510 # define SM501_MMIO_BASE        CFG_CS1_START + 0x03E00000
 511 #endif /* CONFIG_TQM5200 */
 512
 513 #define CFG_CS_BURST            0x00000000
 514 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for     */
 515                                                 /*  flash and SM501     */
 516
 517 #define CFG_RESET_ADDRESS       0xff000000
 518
 519 /*
 520  * USB stuff
 521  */
 522 #define CONFIG_USB_CLOCK        0x0001BBBB
 523 #define CONFIG_USB_CONFIG       0x00002000      /* we're using Port 2   */
 524
 525 /*
 526  * IDE/ATA stuff Supports IDE harddisk
 527  */
 528 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 529
 530 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
 531 #undef  CONFIG_IDE_LED                  /* LED for ide    not supported */
 532
 533 #define CONFIG_IDE_RESET                /* reset for ide      supported */
 534 #define CONFIG_IDE_PREINIT
 535
 536 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 537 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 538
 539 #define CFG_ATA_IDE0_OFFSET     0x0000
 540
 541 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 542
 543 /* Offset for data I/O */
 544 #define CFG_ATA_DATA_OFFSET     (0x0060)
 545
 546 /* Offset for normal register accesses */
 547 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 548
 549 /* Offset for alternate registers */
 550 #define CFG_ATA_ALT_OFFSET      (0x005C)
 551
 552 /* Interval between registers */
 553 #define CFG_ATA_STRIDE          4
 554
 555 #endif /* __CONFIG_H */