include/configs/MPC8360ERDK.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1 /* E300 family */
  24 #define CONFIG_QE               1 /* Has QE */
  25 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  26 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  27 #define CONFIG_MPC8360ERDK      1 /* MPC8360ERDK board specific */
  28
  29 /*
  30  * System Clock Setup
  31  */
  32 #ifdef CONFIG_CLKIN_33MHZ
  33 #define CONFIG_83XX_CLKIN               33333333
  34 #define CONFIG_SYS_CLK_FREQ             33333333
  35 #define PCI_33M                         1
  36 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK  HRCWL_CSB_TO_CLKIN_10X1
  37 #else
  38 #define CONFIG_83XX_CLKIN               66000000
  39 #define CONFIG_SYS_CLK_FREQ             66000000
  40 #define PCI_66M                         1
  41 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK  HRCWL_CSB_TO_CLKIN_5X1
  42 #endif /* CONFIG_CLKIN_33MHZ */
  43
  44 /*
  45  * Hardware Reset Configuration Word
  46  */
  47 #define CFG_HRCW_LOW (\
  48         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  49         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  50         HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
  51         HRCWL_CORE_TO_CSB_2X1 |\
  52         HRCWL_CE_TO_PLL_1X15)
  53
  54 #define CFG_HRCW_HIGH (\
  55         HRCWH_PCI_HOST |\
  56         HRCWH_PCI1_ARBITER_ENABLE |\
  57         HRCWH_PCICKDRV_ENABLE |\
  58         HRCWH_CORE_ENABLE |\
  59         HRCWH_FROM_0X00000100 |\
  60         HRCWH_BOOTSEQ_DISABLE |\
  61         HRCWH_SW_WATCHDOG_DISABLE |\
  62         HRCWH_ROM_LOC_LOCAL_16BIT |\
  63         HRCWH_SECONDARY_DDR_DISABLE |\
  64         HRCWH_BIG_ENDIAN |\
  65         HRCWH_LALE_EARLY)
  66
  67 /*
  68  * System IO Config
  69  */
  70 #define CFG_SICRH               0x00000000
  71 #define CFG_SICRL               0x40000000
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  74 #define CONFIG_BOARD_EARLY_INIT_R
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CFG_IMMR                0xE0000000
  80
  81 /*
  82  * DDR Setup
  83  */
  84 #define CFG_DDR_BASE            0x00000000 /* DDR is system memory */
  85 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  86 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
  87 #define CFG_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
  88                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  89
  90 #define CFG_83XX_DDR_USES_CS0
  91
  92 #define CONFIG_DDR_ECC          /* support DDR ECC function */
  93 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
  94
  95 /*
  96  * DDRCDR - DDR Control Driver Register
  97  */
  98 #define CFG_DDRCDR_VALUE        0x80080001
  99
 100 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 101
 102 /*
 103  * Manually set up DDR parameters
 104  */
 105 #define CONFIG_DDR_II
 106 #define CFG_DDR_SIZE            256 /* MB */
 107 #define CFG_DDR_CS0_BNDS        0x0000000f
 108 #define CFG_DDR_CS0_CONFIG      (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
 109                                  CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 110 #define CFG_DDR_SDRAM_CFG       (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
 111 #define CFG_DDR_SDRAM_CFG2      0x00001000
 112 #define CFG_DDR_CLK_CNTL        (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 113 #define CFG_DDR_INTERVAL        ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 114                                  (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 115 #define CFG_DDR_MODE            0x47800432
 116 #define CFG_DDR_MODE2           0x8000c000
 117
 118 #define CFG_DDR_TIMING_0        ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 119                                  (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 120                                  (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 121                                  (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 122                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 123                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 124                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 125                                  (0 << TIMING_CFG0_RWT_SHIFT))
 126
 127 #define CFG_DDR_TIMING_1        ((      TIMING_CFG1_CASLAT_30) | \
 128                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 129                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 130                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 131                                  (10 << TIMING_CFG1_REFREC_SHIFT) | \
 132                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 133                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 134                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 135
 136 #define CFG_DDR_TIMING_2        ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 137                                  (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 138                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 139                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 140                                  (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 141                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 142                                  (0 << TIMING_CFG2_CPO_SHIFT))
 143
 144 #define CFG_DDR_TIMING_3        0x00000000
 145
 146 /*
 147  * Memory test
 148  */
 149 #undef CFG_DRAM_TEST            /* memory test, takes time */
 150 #define CFG_MEMTEST_START       0x00000000 /* memtest region */
 151 #define CFG_MEMTEST_END         0x00100000
 152
 153 /*
 154  * The reserved memory
 155  */
 156 #define CFG_MONITOR_BASE        TEXT_BASE /* start of monitor */
 157 #define CFG_FLASH_BASE          0xFF800000 /* FLASH base address */
 158
 159 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 160 #define CFG_RAMBOOT
 161 #else
 162 #undef  CFG_RAMBOOT
 163 #endif
 164
 165 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 166 #define CFG_MALLOC_LEN          (128 * 1024) /* Reserved for malloc */
 167
 168 /*
 169  * Initial RAM Base Address Setup
 170  */
 171 #define CFG_INIT_RAM_LOCK       1
 172 #define CFG_INIT_RAM_ADDR       0xE6000000 /* Initial RAM address */
 173 #define CFG_INIT_RAM_END        0x1000 /* End of used area in RAM */
 174 #define CFG_GBL_DATA_SIZE       0x100 /* num bytes initial data */
 175 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 176
 177 /*
 178  * Local Bus Configuration & Clock Setup
 179  */
 180 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_4)
 181 #define CFG_LBC_LBCR            0x00000000
 182
 183 /*
 184  * FLASH on the Local Bus
 185  */
 186 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 187 #define CFG_FLASH_CFI_DRIVER    /* use the CFI driver */
 188 #define CFG_FLASH_SIZE          8 /* max FLASH size is 32M */
 189 #define CFG_FLASH_PROTECTION    1 /* Use intel Flash protection. */
 190
 191 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE /* Window base at flash base */
 192 #define CFG_LBLAWAR0_PRELIM     0x80000018 /* 32MB window size */
 193
 194 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE | /* Flash Base address */ \
 195                         (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 196                         BR_V)   /* valid */
 197 #define CFG_OR0_PRELIM          ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 198                                 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
 199                                 OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 200                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 201
 202 #define CFG_MAX_FLASH_BANKS     1 /* number of banks */
 203 #define CFG_MAX_FLASH_SECT      256 /* max sectors per device */
 204
 205 #undef  CFG_FLASH_CHECKSUM
 206
 207 /*
 208  * NAND flash on the local bus
 209  */
 210 #define CFG_NAND_BASE           0x60000000
 211 #define CONFIG_CMD_NAND         1
 212 #define CONFIG_NAND_FSL_UPM     1
 213 #define CFG_MAX_NAND_DEVICE     1
 214 #define NAND_MAX_CHIPS          1
 215 #define CONFIG_MTD_NAND_VERIFY_WRITE
 216
 217 #define CFG_LBLAWBAR1_PRELIM    CFG_NAND_BASE
 218 #define CFG_LBLAWAR1_PRELIM     0x8000001b /* Access window size 4K */
 219
 220 /* Port size 8 bit, UPMA */
 221 #define CFG_BR1_PRELIM          (CFG_NAND_BASE | 0x00000881)
 222 #define CFG_OR1_PRELIM          0xfc000001
 223
 224 /*
 225  * Fujitsu MB86277 (MINT) graphics controller
 226  */
 227 #define CFG_VIDEO_BASE          0x70000000
 228
 229 #define CFG_LBLAWBAR2_PRELIM    CFG_VIDEO_BASE
 230 #define CFG_LBLAWAR2_PRELIM     0x80000019 /* Access window size 64MB */
 231
 232 /* Port size 32 bit, UPMB */
 233 #define CFG_BR2_PRELIM          (CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
 234 #define CFG_OR2_PRELIM          0xfc000001 /* (64MB, EAD=1) */
 235
 236 /*
 237  * Serial Port
 238  */
 239 #define CONFIG_CONS_INDEX       1
 240 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 241 #define CFG_NS16550
 242 #define CFG_NS16550_SERIAL
 243 #define CFG_NS16550_REG_SIZE    1
 244 #define CFG_NS16550_CLK         get_bus_freq(0)
 245
 246 #define CFG_BAUDRATE_TABLE  \
 247         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
 248
 249 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 250 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 251
 252 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 253 /* Use the HUSH parser */
 254 #define CFG_HUSH_PARSER
 255 #ifdef  CFG_HUSH_PARSER
 256 #define CFG_PROMPT_HUSH_PS2 "> "
 257 #endif
 258
 259 /* Pass open firmware flat tree */
 260 #define CONFIG_OF_LIBFDT        1
 261 #define CONFIG_OF_BOARD_SETUP   1
 262 #define CONFIG_OF_STDOUT_VIA_ALIAS
 263
 264 /* I2C */
 265 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 266 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 267 #define CONFIG_FSL_I2C
 268 #define CONFIG_I2C_MULTI_BUS
 269 #define CONFIG_I2C_CMD_TREE
 270 #define CFG_I2C_SPEED   400000  /* I2C speed and slave address */
 271 #define CFG_I2C_SLAVE   0x7F
 272 #define CFG_I2C_NOPROBES        {{0x52}} /* Don't probe these addrs */
 273 #define CFG_I2C_OFFSET  0x3000
 274 #define CFG_I2C2_OFFSET 0x3100
 275
 276 /*
 277  * General PCI
 278  * Addresses are mapped 1-1.
 279  */
 280 #define CONFIG_PCI
 281 #define CONFIG_83XX_GENERIC_PCI 1
 282
 283 #define CFG_PCI1_MEM_BASE       0x80000000
 284 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 285 #define CFG_PCI1_MEM_SIZE       0x10000000 /* 256M */
 286 #define CFG_PCI1_MMIO_BASE      0x90000000
 287 #define CFG_PCI1_MMIO_PHYS      CFG_PCI1_MMIO_BASE
 288 #define CFG_PCI1_MMIO_SIZE      0x10000000 /* 256M */
 289 #define CFG_PCI1_IO_BASE        0xE0300000
 290 #define CFG_PCI1_IO_PHYS        0xE0300000
 291 #define CFG_PCI1_IO_SIZE        0x100000 /* 1M */
 292
 293 #ifdef CONFIG_PCI
 294
 295 #define CONFIG_NET_MULTI
 296 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 297
 298 #undef CONFIG_EEPRO100
 299 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 300 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 301
 302 #endif  /* CONFIG_PCI */
 303
 304
 305 #ifndef CONFIG_NET_MULTI
 306 #define CONFIG_NET_MULTI        1
 307 #endif
 308
 309 /*
 310  * QE UEC ethernet configuration
 311  */
 312 #define CONFIG_UEC_ETH
 313 #define CONFIG_ETHPRIME         "FSL UEC0"
 314
 315 #define CONFIG_UEC_ETH1         /* GETH1 */
 316
 317 #ifdef CONFIG_UEC_ETH1
 318 #define CFG_UEC1_UCC_NUM        0       /* UCC1 */
 319 #define CFG_UEC1_RX_CLK         QE_CLK_NONE
 320 #define CFG_UEC1_TX_CLK         QE_CLK9
 321 #define CFG_UEC1_ETH_TYPE       GIGA_ETH
 322 #define CFG_UEC1_PHY_ADDR       2
 323 #define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 324 #endif
 325
 326 #define CONFIG_UEC_ETH2         /* GETH2 */
 327
 328 #ifdef CONFIG_UEC_ETH2
 329 #define CFG_UEC2_UCC_NUM        1       /* UCC2 */
 330 #define CFG_UEC2_RX_CLK         QE_CLK_NONE
 331 #define CFG_UEC2_TX_CLK         QE_CLK4
 332 #define CFG_UEC2_ETH_TYPE       GIGA_ETH
 333 #define CFG_UEC2_PHY_ADDR       4
 334 #define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 335 #endif
 336
 337 /*
 338  * Environment
 339  */
 340
 341 #ifndef CFG_RAMBOOT
 342 #define CFG_ENV_IS_IN_FLASH     1
 343 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 344 #define CFG_ENV_SECT_SIZE       0x20000 /* 128K(one sector) for env */
 345 #define CFG_ENV_SIZE            0x20000
 346 #else /* CFG_RAMBOOT */
 347 #define CFG_NO_FLASH            1       /* Flash is not usable now */
 348 #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 349 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 350 #define CFG_ENV_SIZE            0x2000
 351 #endif /* CFG_RAMBOOT */
 352
 353 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 354 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 355
 356 /*
 357  * BOOTP options
 358  */
 359 #define CONFIG_BOOTP_BOOTFILESIZE
 360 #define CONFIG_BOOTP_BOOTPATH
 361 #define CONFIG_BOOTP_GATEWAY
 362 #define CONFIG_BOOTP_HOSTNAME
 363
 364
 365 /*
 366  * Command line configuration.
 367  */
 368 #include <config_cmd_default.h>
 369
 370 #define CONFIG_CMD_PING
 371 #define CONFIG_CMD_I2C
 372 #define CONFIG_CMD_ASKENV
 373 #define CONFIG_CMD_DHCP
 374
 375 #if defined(CONFIG_PCI)
 376 #define CONFIG_CMD_PCI
 377 #endif
 378
 379 #if defined(CFG_RAMBOOT)
 380 #undef CONFIG_CMD_ENV
 381 #undef CONFIG_CMD_LOADS
 382 #endif
 383
 384 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 385
 386 /*
 387  * Miscellaneous configurable options
 388  */
 389 #define CFG_LONGHELP            /* undef to save memory */
 390 #define CFG_LOAD_ADDR           0x2000000 /* default load address */
 391 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 392
 393 #if defined(CONFIG_CMD_KGDB)
 394         #define CFG_CBSIZE      1024 /* Console I/O Buffer Size */
 395 #else
 396         #define CFG_CBSIZE      256 /* Console I/O Buffer Size */
 397 #endif
 398
 399 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 400 #define CFG_MAXARGS     16              /* max number of command args */
 401 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 402 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 403
 404 /*
 405  * For booting Linux, the board info and command line data
 406  * have to be in the first 8 MB of memory, since this is
 407  * the maximum mapped by the Linux kernel during initialization.
 408  */
 409 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 410
 411 /*
 412  * Core HID Setup
 413  */
 414 #define CFG_HID0_INIT           0x000000000
 415 #define CFG_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
 416 #define CFG_HID2                HID2_HBE
 417
 418 /*
 419  * MMU Setup
 420  */
 421
 422 /* DDR: cache cacheable */
 423 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 424 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 425 #define CFG_DBAT0L      CFG_IBAT0L
 426 #define CFG_DBAT0U      CFG_IBAT0U
 427
 428 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 429 #define CFG_IBAT1L      (CFG_IMMR | BATL_PP_10 | \
 430                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 431 #define CFG_IBAT1U      (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 432 #define CFG_DBAT1L      CFG_IBAT1L
 433 #define CFG_DBAT1U      CFG_IBAT1U
 434
 435 /* NAND: cache-inhibit and guarded */
 436 #define CFG_IBAT2L      (CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 437                          BATL_GUARDEDSTORAGE)
 438 #define CFG_IBAT2U      (CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 439 #define CFG_DBAT2L      CFG_IBAT2L
 440 #define CFG_DBAT2U      CFG_IBAT2U
 441
 442 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 443 #define CFG_IBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 444 #define CFG_IBAT3U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 445 #define CFG_DBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | \
 446                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 447 #define CFG_DBAT3U      CFG_IBAT3U
 448
 449 /* Stack in dcache: cacheable, no memory coherence */
 450 #define CFG_IBAT4L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 451 #define CFG_IBAT4U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 452 #define CFG_DBAT4L      CFG_IBAT4L
 453 #define CFG_DBAT4U      CFG_IBAT4U
 454
 455 #define CFG_IBAT5L      (CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
 456                          BATL_GUARDEDSTORAGE)
 457 #define CFG_IBAT5U      (CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 458 #define CFG_DBAT5L      CFG_IBAT5L
 459 #define CFG_DBAT5U      CFG_IBAT5U
 460
 461 #ifdef CONFIG_PCI
 462 /* PCI MEM space: cacheable */
 463 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 464 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 465 #define CFG_DBAT6L      CFG_IBAT6L
 466 #define CFG_DBAT6U      CFG_IBAT6U
 467 /* PCI MMIO space: cache-inhibit and guarded */
 468 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 469                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 470 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 471 #define CFG_DBAT7L      CFG_IBAT7L
 472 #define CFG_DBAT7U      CFG_IBAT7U
 473 #else /* CONFIG_PCI */
 474 #define CFG_IBAT6L      (0)
 475 #define CFG_IBAT6U      (0)
 476 #define CFG_IBAT7L      (0)
 477 #define CFG_IBAT7U      (0)
 478 #define CFG_DBAT6L      CFG_IBAT6L
 479 #define CFG_DBAT6U      CFG_IBAT6U
 480 #define CFG_DBAT7L      CFG_IBAT7L
 481 #define CFG_DBAT7U      CFG_IBAT7U
 482 #endif /* CONFIG_PCI */
 483
 484 /*
 485  * Internal Definitions
 486  *
 487  * Boot Flags
 488  */
 489 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 490 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 491
 492 #if defined(CONFIG_CMD_KGDB)
 493 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 494 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 495 #endif
 496
 497 /*
 498  * Environment Configuration
 499  */
 500 #define CONFIG_ENV_OVERWRITE
 501
 502 #if defined(CONFIG_UEC_ETH)
 503 #define CONFIG_HAS_ETH0
 504 #define CONFIG_HAS_ETH1
 505 #define CONFIG_HAS_ETH2
 506 #define CONFIG_HAS_ETH3
 507 #define CONFIG_ETHADDR  00:04:9f:ef:01:01
 508 #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
 509 #define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
 510 #define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
 511 #endif
 512
 513 #define CONFIG_BAUDRATE 115200
 514
 515 #define CONFIG_LOADADDR a00000
 516 #define CONFIG_HOSTNAME mpc8360erdk
 517 #define CONFIG_BOOTFILE uImage
 518
 519 #define CONFIG_IPADDR           10.0.0.99
 520 #define CONFIG_SERVERIP         10.0.0.2
 521 #define CONFIG_GATEWAYIP        10.0.0.2
 522 #define CONFIG_NETMASK          255.255.255.0
 523 #define CONFIG_ROOTPATH         /nfsroot/
 524
 525 #define CONFIG_BOOTDELAY 2      /* -1 disables auto-boot */
 526 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 527
 528 #define CONFIG_EXTRA_ENV_SETTINGS \
 529    "netdev=eth0\0"\
 530    "consoledev=ttyS0\0"\
 531    "loadaddr=a00000\0"\
 532    "fdtaddr=900000\0"\
 533    "fdtfile=dtb\0"\
 534    "fsfile=fs\0"\
 535    "ubootfile=u-boot.bin\0"\
 536    "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
 537    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
 538                 "$mtdparts panic=1\0"\
 539    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
 540    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
 541                 "$gatewayip:$netmask:$hostname:$netdev:off "\
 542                 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
 543    "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
 544                 "rootfstype=jffs2 rw\0"\
 545    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
 546    "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
 547    "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
 548    "tftp_get_fs=tftp c00000 $fsfile\0"\
 549    "nand_erase_kernel=nand erase 0 400000\0"\
 550    "nand_erase_dtb=nand erase 400000 20000\0"\
 551    "nand_erase_fs=nand erase 420000 3be0000\0"\
 552    "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
 553    "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
 554    "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
 555    "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
 556    "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
 557    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
 558                 "cp.b 100000 ff800000 $filesize\0"\
 559    "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
 560                 "nand_write_kernel\0"\
 561    "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
 562    "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
 563    "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
 564                 "nand_reflash_fs\0"\
 565    "boot_m=bootm $loadaddr - $fdtaddr\0"\
 566    "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
 567    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
 568                 "boot_m\0"\
 569    "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
 570                 "boot_m\0"\
 571    ""
 572
 573 #define CONFIG_BOOTCOMMAND "run dhcpboot"
 574
 575 #endif /* __CONFIG_H */