board/lantec/lantec.c

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * (C) Copyright 2001
   5  * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
   6  * Bruno Achauer, Exet AG, bruno@exet-ag.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * Derived from ../tqm8xx/tqm8xx.c
  29  */
  30
  31 #include <common.h>
  32 #include <mpc8xx.h>
  33
  34 /* ------------------------------------------------------------------------- */
  35
  36 static long int dram_size (long int, long int *, long int);
  37
  38 /* ------------------------------------------------------------------------- */
  39
  40 #define _NOT_USED_      0xFFFFFFFF
  41
  42 const uint sdram_table[] = {
  43         /*
  44          * Single Read. (Offset 0 in UPMA RAM)
  45          */
  46         0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
  47         0x1ff77c47,             /* last */
  48         /*
  49          * SDRAM Initialization (offset 5 in UPMA RAM)
  50          *
  51          * This is no UPM entry point. The following definition uses
  52          * the remaining space to establish an initialization
  53          * sequence, which is executed by a RUN command.
  54          *
  55          */
  56         0x1ff77c35, 0xefeabc34, 0x1fb57c35,     /* last */
  57         /*
  58          * Burst Read. (Offset 8 in UPMA RAM)
  59          */
  60         0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
  61         0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
  62         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  63         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64         /*
  65          * Single Write. (Offset 18 in UPMA RAM)
  66          */
  67         0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
  68         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  69         /*
  70          * Burst Write. (Offset 20 in UPMA RAM)
  71          */
  72         0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  73         0xf0affc00, 0xe1bbbc04, 0x1ff77c47,     /* last */
  74         _NOT_USED_,
  75         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  76         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  77         /*
  78          * Refresh  (Offset 30 in UPMA RAM)
  79          */
  80         0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  81         0xfffffc84, 0xfffffc07, 0xfffffc07,     /* last */
  82         _NOT_USED_,
  83         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  84         /*
  85          * Exception. (Offset 3c in UPMA RAM)
  86          */
  87         0x7ffffc07,             /* last */
  88         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  89 };
  90
  91 /* ------------------------------------------------------------------------- */
  92
  93
  94 /*
  95  * Check Board Identity:
  96  *
  97  * Test TQ ID string (TQM8xx...)
  98  * If present, check for "L" type (no second DRAM bank),
  99  * otherwise "L" type is assumed as default.
 100  *
 101  * Return 1 for "L" type, 0 else.
 102  */
 103
 104 int checkboard (void)
 105 {
 106         printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
 107         return 0;
 108 }
 109
 110 /* ------------------------------------------------------------------------- */
 111
 112 long int initdram (int board_type)
 113 {
 114         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 115         volatile memctl8xx_t *memctl = &immap->im_memctl;
 116         long int size_b0;
 117         int i;
 118
 119         /*
 120          * Configure UPMA for SDRAM
 121          */
 122         upmconfig (UPMA, (uint *) sdram_table,
 123                    sizeof (sdram_table) / sizeof (uint));
 124
 125         memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
 126
 127         /* burst length=4, burst type=sequential, CAS latency=2 */
 128         memctl->memc_mar = 0x00000088;
 129
 130         /*
 131          * Map controller bank 3 to the SDRAM bank at preliminary address.
 132          */
 133         memctl->memc_or3 = CFG_OR3_PRELIM;
 134         memctl->memc_br3 = CFG_BR3_PRELIM;
 135
 136         /* initialize memory address register */
 137         memctl->memc_mamr = CFG_MAMR_8COL;      /* refresh not enabled yet */
 138
 139         /* mode initialization (offset 5) */
 140         udelay (200);           /* 0x80006105 */
 141         memctl->memc_mcr =
 142                 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
 143
 144         /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
 145         udelay (1);             /* 0x80006130 */
 146         memctl->memc_mcr =
 147                 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
 148         udelay (1);             /* 0x80006130 */
 149         memctl->memc_mcr =
 150                 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
 151
 152         udelay (1);             /* 0x80006106 */
 153         memctl->memc_mcr =
 154                 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
 155
 156         memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
 157
 158         udelay (200);
 159
 160         /* Need at least 10 DRAM accesses to stabilize */
 161         for (i = 0; i < 10; ++i) {
 162                 volatile unsigned long *addr =
 163                         (volatile unsigned long *) SDRAM_BASE3_PRELIM;
 164                 unsigned long val;
 165
 166                 val = *(addr + i);
 167                 *(addr + i) = val;
 168         }
 169
 170         /*
 171          * Check Bank 0 Memory Size for re-configuration
 172          */
 173         size_b0 = dram_size (CFG_MAMR_8COL,
 174                              (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 175
 176         memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
 177
 178         /*
 179          * Final mapping:
 180          */
 181
 182         memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 183         memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 184         udelay (1000);
 185
 186         return (size_b0);
 187 }
 188
 189 /* ------------------------------------------------------------------------- */
 190
 191 /*
 192  * Check memory range for valid RAM. A simple memory test determines
 193  * the actually available RAM size between addresses `base' and
 194  * `base + maxsize'. Some (not all) hardware errors are detected:
 195  * - short between address lines
 196  * - short between data lines
 197  */
 198
 199 static long int dram_size (long int mamr_value, long int *base,
 200                            long int maxsize)
 201 {
 202         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 203         volatile memctl8xx_t *memctl = &immap->im_memctl;
 204
 205         memctl->memc_mamr = mamr_value;
 206
 207         return (get_ram_size (base, maxsize));
 208 }