2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the FIC HXD8 by Harald Welte <laforge@openmoko.org>
8 * (C) Copyright 2007 by OpenMoko, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* some parameters for the board */
38 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
40 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
44 #define BWSCON 0x48000000
53 #define B1_BWSCON (DW32)
54 #define B2_BWSCON (DW16)
55 #define B3_BWSCON (DW16 + WAIT + UBLB)
56 #define B4_BWSCON (DW16)
57 #define B5_BWSCON (DW16)
58 #define B6_BWSCON (DW32)
59 #define B7_BWSCON (DW32)
62 #define B0_Tacs 0x0 /* 0clk */
63 #define B0_Tcos 0x0 /* 0clk */
64 #define B0_Tacc 0x7 /* 14clk */
65 #define B0_Tcoh 0x0 /* 0clk */
66 #define B0_Tah 0x0 /* 0clk */
68 #define B0_PMC 0x0 /* normal */
71 #define B1_Tacs 0x0 /* 0clk */
72 #define B1_Tcos 0x0 /* 0clk */
73 #define B1_Tacc 0x7 /* 14clk */
74 #define B1_Tcoh 0x0 /* 0clk */
75 #define B1_Tah 0x0 /* 0clk */
87 #define B3_Tacs 0x0 /* 0clk */
88 #define B3_Tcos 0x3 /* 4clk */
89 #define B3_Tacc 0x7 /* 14clk */
90 #define B3_Tcoh 0x1 /* 1clk */
91 #define B3_Tah 0x0 /* 0clk */
92 #define B3_Tacp 0x3 /* 6clk */
93 #define B3_PMC 0x0 /* normal */
95 #define B4_Tacs 0x0 /* 0clk */
96 #define B4_Tcos 0x0 /* 0clk */
97 #define B4_Tacc 0x7 /* 14clk */
98 #define B4_Tcoh 0x0 /* 0clk */
99 #define B4_Tah 0x0 /* 0clk */
101 #define B4_PMC 0x0 /* normal */
103 #define B5_Tacs 0x0 /* 0clk */
104 #define B5_Tcos 0x0 /* 0clk */
105 #define B5_Tacc 0x7 /* 14clk */
106 #define B5_Tcoh 0x0 /* 0clk */
107 #define B5_Tah 0x0 /* 0clk */
109 #define B5_PMC 0x0 /* normal */
111 #define B6_MT 0x3 /* SDRAM */
112 #define B6_Trcd 0x1 /* 3clk */
113 #define B6_SCAN 0x2 /* 10bit */
115 #define B7_MT 0x3 /* SDRAM */
116 #define B7_Trcd 0x1 /* 3clk */
117 #define B7_SCAN 0x1 /* 9bit */
119 /* REFRESH parameter */
120 #define REFEN 0x1 /* Refresh enable */
121 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
122 #define Trp 0x1 /* 3clk */
123 #define Trc 0x3 /* 7clk */
124 #define Tchr 0x2 /* 3clk */
125 #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
126 /**************************************/
133 /* memory control configuration */
134 /* make r0 relative the current location so that it */
135 /* reads SMRDATA out of FLASH rather than memory ! */
139 ldr r1, =BWSCON /* Bus Width Status Controller */
147 /* setup asynchronous bus mode */
148 mrc p15, 0, r1 ,c1 ,c0, 0
149 orr r1, r1, #0xc0000000
150 mcr p15, 0, r1, c1, c0, 0
152 /* everything is fine now */
156 /* the literal pools origin */
159 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
160 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
161 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
162 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
163 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
164 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
165 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
166 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
167 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
168 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)