2 * (C) Copyright 2005, Embedded Alley Solutions, Inc.
3 * Dan Malek, <dan@embeddedalley.com>
5 * Updates for Silicon Tx GP3 SSA
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/processor.h>
35 #include <asm/immap_85xx.h>
38 #include <spd_sdram.h>
41 long int fixed_sdram (void);
44 * I/O Port configuration table
46 * if conf is 1, then that port pin will be configured at boot time
47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 const iop_conf_t iop_conf_tab
[4][32] = {
52 /* Port A configuration */
53 { /* conf ppar psor pdir podr pdat */
54 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
55 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
56 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
57 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
58 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
59 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
60 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
61 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
62 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
63 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
64 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
65 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
66 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
67 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
68 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
69 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
70 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
71 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
72 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
73 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
74 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
75 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
76 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
77 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
78 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
79 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
80 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
81 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
82 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
83 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
84 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
85 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
88 /* Port B configuration */
89 { /* conf ppar psor pdir podr pdat */
90 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
91 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
92 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
93 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
94 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
95 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
96 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
97 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
98 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
99 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
100 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
101 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
102 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
103 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
104 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
105 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
106 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
107 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
108 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
109 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
110 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
125 { /* conf ppar psor pdir podr pdat */
126 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
127 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
128 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
129 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
130 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
131 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
132 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
133 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
134 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
135 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
136 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
137 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
138 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
139 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
140 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
141 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
142 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
143 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
144 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
145 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
146 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
147 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
148 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
149 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
150 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
151 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
152 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
153 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
154 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
155 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
156 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
157 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
161 { /* conf ppar psor pdir podr pdat */
162 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
163 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
164 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
165 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
166 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
167 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
168 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
169 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
170 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
171 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
172 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
173 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
174 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
175 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
176 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
177 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
178 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
184 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
185 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
186 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
187 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
188 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
189 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
197 static uint64_t next_led_update
;
203 volatile uint
*blatch
;
207 blatch
= (volatile uint
*)CFG_LBC_CFGLATCH_BASE
;
209 /* reset Giga bit Ethernet port if needed here */
212 *blatch
&= ~0x000000c0;
217 for (i
=0; i
<1000; i
++)
220 *blatch
= 0x000000c1; /* Light one led, too */
223 #if 0 /* This is the port we really want to use for debugging. */
224 /* reset the CPM FEC port */
225 #if (CONFIG_ETHER_INDEX == 2)
226 bcsr
->bcsr2
&= ~FETH2_RST
;
228 bcsr
->bcsr2
|= FETH2_RST
;
230 #elif (CONFIG_ETHER_INDEX == 3)
231 bcsr
->bcsr3
&= ~FETH3_RST
;
233 bcsr
->bcsr3
|= FETH3_RST
;
236 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
238 miiphy_reset("FCC1 ETHERNET", 0x0);
240 /* change PHY address to 0x02 */
241 bb_miiphy_write(NULL
, 0, PHY_MIPSCR
, 0xf028);
243 bb_miiphy_write(NULL
, 0x02, PHY_BMCR
,
244 PHY_BMCR_AUTON
| PHY_BMCR_RST_NEG
);
245 #endif /* CONFIG_MII */
250 board_early_init_f(void)
252 #if defined(CONFIG_PCI)
253 volatile ccsr_pcix_t
*pci
= (void *)(CFG_MPC85xx_PCIX_ADDR
);
255 pci
->peer
&= 0xffffffdf; /* disable master abort */
258 /* Why is the phy reset done _after_ the ethernet
259 * initialization in lib_ppc/board.c?
260 * Do it here so it's done before the TSECs are used.
270 printf ("Board: Silicon Tx GPPP SSA Board\n");
274 /* Blinkin' LEDS for Robert.
277 show_activity(int flag
)
279 volatile uint
*blatch
;
281 if (next_led_update
> get_ticks())
284 blatch
= (volatile uint
*)CFG_LBC_CFGLATCH_BASE
;
289 *blatch
= (0xc0 | led_bit
);
291 next_led_update
+= (get_tbclk() / 4);
295 initdram (int board_type
)
299 #if defined(CONFIG_DDR_DLL)
301 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
302 uint temp_ddrdll
= 0;
304 /* Work around to stabilize DDR DLL */
305 temp_ddrdll
= gur
->ddrdllcr
;
306 gur
->ddrdllcr
= ((temp_ddrdll
& 0xff) << 16) | 0x80000000;
307 asm("sync;isync;msync");
311 dram_size
= spd_sdram ();
313 #if defined(CONFIG_DDR_ECC)
314 /* Initialize and enable DDR ECC.
316 ddr_enable_ecc(dram_size
);
323 #if defined(CFG_DRAM_TEST)
326 uint
*pstart
= (uint
*) CFG_MEMTEST_START
;
327 uint
*pend
= (uint
*) CFG_MEMTEST_END
;
330 printf("SDRAM test phase 1:\n");
331 for (p
= pstart
; p
< pend
; p
++)
334 for (p
= pstart
; p
< pend
; p
++) {
335 if (*p
!= 0xaaaaaaaa) {
336 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
341 printf("SDRAM test phase 2:\n");
342 for (p
= pstart
; p
< pend
; p
++)
345 for (p
= pstart
; p
< pend
; p
++) {
346 if (*p
!= 0x55555555) {
347 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
352 printf("SDRAM test passed.\n");
357 #if defined(CONFIG_PCI)
360 * Initialize PCI Devices, report devices found.
363 #ifndef CONFIG_PCI_PNP
364 static struct pci_config_table pci_stxgp3_config_table
[] = {
365 { PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
366 PCI_IDSEL_NUMBER
, PCI_ANY_ID
,
367 pci_cfgfunc_config_device
, { PCI_ENET0_IOADDR
,
369 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
376 static struct pci_controller hose
[] = {
377 #ifndef CONFIG_PCI_PNP
378 { config_table
: pci_stxgp3_config_table
,},
382 #ifdef CONFIG_MPC85XX_PCI2
387 #endif /* CONFIG_PCI */
394 extern void pci_mpc85xx_init(struct pci_controller
*hose
);
396 pci_mpc85xx_init(hose
);
397 #endif /* CONFIG_PCI */